Palmer Dabbelt c988de4119 RISC-V: Fix a memory leak when realizing a sifive_e ... Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(), where a pair of recently added MemoryRegion instances would not be freed if there were errors elsewhere in the function. The fix here is to simply not use dynamic allocation for these instances: there's always one of each in SiFiveESoCState, so instead we just include them within the struct. Fixes: 30efbf330a ("SiFive RISC-V GPIO Device") Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>		2019-06-23 23:44:42 -07:00
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riscv_hart.h	RISC-V HART Array	2018-03-07 08:30:28 +13:00
riscv_htif.h	RISC-V HTIF Console	2018-03-07 08:30:28 +13:00
sifive_clint.h	RISC-V: Replace hardcoded constants with enum values	2018-05-06 10:39:38 +12:00
sifive_e.h	RISC-V: Fix a memory leak when realizing a sifive_e	2019-06-23 23:44:42 -07:00
sifive_gpio.h	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
sifive_plic.h	Clean up decorations and whitespace around header guards	2019-05-13 08:58:55 +02:00
sifive_prci.h	sifive_prci: Read and write PRCI registers	2019-06-23 23:44:41 -07:00
sifive_test.h	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.h	riscv: plic: Fix incorrect irq calculation	2019-04-04 16:36:19 -07:00
sifive_uart.h	sifive_uart: Implement interrupt pending register	2018-12-20 12:08:43 -08:00
spike.h	RISC-V: Make some header guards more specific	2018-05-06 10:39:38 +12:00
virt.h	target/riscv: Add a base 32 and 64 bit CPU	2019-05-24 12:09:23 -07:00