mirror of https://github.com/xemu-project/xemu.git
285 lines
7.4 KiB
C
285 lines
7.4 KiB
C
/*
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* AMD756 SMBus implementation
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*
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* Copyright (C) 2012 espes
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/xbox/amd_smbus.h"
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#include "hw/i2c/i2c.h"
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#include "hw/i2c/smbus_master.h"
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#include "hw/irq.h"
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// #define DEBUG
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#ifdef DEBUG
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# define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define SMBUS_DPRINTF(format, ...) do { } while (0)
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#endif
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/* AMD756 SMBus address offsets */
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#define SMB_ADDR_OFFSET 0xE0
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#define SMB_IOSIZE 16
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#define SMB_GLOBAL_STATUS 0x0
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#define SMB_GLOBAL_ENABLE 0x2
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#define SMB_HOST_ADDRESS 0x4
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#define SMB_HOST_DATA 0x6
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#define SMB_HOST_COMMAND 0x8
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#define SMB_HOST_BLOCK_DATA 0x9
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#define SMB_HAS_DATA 0xA
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#define SMB_HAS_DEVICE_ADDRESS 0xC
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#define SMB_HAS_HOST_ADDRESS 0xE
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#define SMB_SNOOP_ADDRESS 0xF
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/* AMD756 constants */
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#define AMD756_QUICK 0x00
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#define AMD756_BYTE 0x01
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#define AMD756_BYTE_DATA 0x02
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#define AMD756_WORD_DATA 0x03
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#define AMD756_PROCESS_CALL 0x04
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#define AMD756_BLOCK_DATA 0x05
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/*
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SMBUS event = I/O 28-29 bit 11
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see E0 for the status bits and enabled in E2
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*/
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#define GS_ABRT_STS (1 << 0)
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#define GS_COL_STS (1 << 1)
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#define GS_PRERR_STS (1 << 2)
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#define GS_HST_STS (1 << 3)
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#define GS_HCYC_STS (1 << 4)
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#define GS_TO_STS (1 << 5)
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#define GS_SMB_STS (1 << 11)
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#define GS_CLEAR_STS (GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS \
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| GS_HCYC_STS | GS_TO_STS)
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#define GE_CYC_TYPE_MASK (7)
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#define GE_HOST_STC (1 << 3)
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#define GE_HCYC_EN (1 << 4)
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#define GE_ABORT (1 << 5)
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static void amd756_smb_transaction(AMD756SMBus *s)
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{
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uint8_t prot = s->smb_ctl & GE_CYC_TYPE_MASK;
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = (s->smb_addr >> 1) & 0x7f;
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I2CBus *bus = s->smbus;
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int ret;
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SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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switch (prot) {
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case AMD756_QUICK:
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ret = smbus_quick_command(bus, addr, read);
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goto done;
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break;
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case AMD756_BYTE:
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if (read) {
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ret = smbus_receive_byte(bus, addr);
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goto data8;
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} else {
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ret = smbus_send_byte(bus, addr, cmd);
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goto done;
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}
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break;
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case AMD756_BYTE_DATA:
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if (read) {
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ret = smbus_read_byte(bus, addr, cmd);
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goto data8;
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} else {
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ret = smbus_write_byte(bus, addr, cmd, s->smb_data0);
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goto done;
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}
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break;
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case AMD756_WORD_DATA:
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if (read) {
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ret = smbus_read_word(bus, addr, cmd);
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goto data16;
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} else {
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ret = smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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goto done;
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}
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break;
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case AMD756_BLOCK_DATA:
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if (read) {
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ret = smbus_read_block(bus, addr, cmd, s->smb_data,
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sizeof(s->smb_data), true, true);
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goto data8;
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} else {
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ret = smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0,
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true);
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goto done;
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}
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break;
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default:
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goto error;
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}
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abort();
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data16:
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if (ret < 0) {
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goto error;
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}
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s->smb_data1 = ret >> 8;
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data8:
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if (ret < 0) {
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goto error;
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}
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s->smb_data0 = ret;
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done:
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if (ret < 0) {
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goto error;
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}
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s->smb_stat |= GS_HCYC_STS;
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goto out;
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out:
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return;
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error:
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s->smb_stat |= GS_PRERR_STS;
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return;
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}
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void amd756_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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AMD756SMBus *s = opaque;
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addr &= 0x3f;
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SMBUS_DPRINTF("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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switch (addr) {
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case SMB_GLOBAL_STATUS:
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if (s->irq) {
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/* Raise an irq if interrupts are enabled and a new
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* status is being set */
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if ((s->smb_ctl & GE_HCYC_EN)
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&& ((val & GS_CLEAR_STS)
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& (~(s->smb_stat & GS_CLEAR_STS)))) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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if (val & GS_CLEAR_STS) {
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s->smb_stat = 0;
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s->smb_index = 0;
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} else if (val & GS_HCYC_STS) {
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s->smb_stat = GS_HCYC_STS;
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s->smb_index = 0;
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} else {
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s->smb_stat = GS_HCYC_STS;
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s->smb_index = 0;
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}
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break;
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case SMB_GLOBAL_ENABLE:
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s->smb_ctl = val;
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if (val & GE_ABORT) {
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s->smb_stat |= GS_ABRT_STS;
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}
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if (val & GE_HOST_STC) {
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amd756_smb_transaction(s);
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if (s->irq
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&& (val & GE_HCYC_EN)
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&& (s->smb_stat & GS_CLEAR_STS)) {
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qemu_irq_raise(s->irq);
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}
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}
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break;
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case SMB_HOST_COMMAND:
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s->smb_cmd = val;
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break;
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case SMB_HOST_ADDRESS:
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s->smb_addr = val;
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break;
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case SMB_HOST_DATA:
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s->smb_data0 = val;
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break;
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case SMB_HOST_DATA + 1:
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s->smb_data1 = val;
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break;
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case SMB_HOST_BLOCK_DATA:
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s->smb_data[s->smb_index++] = val;
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if (s->smb_index > 31) {
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s->smb_index = 0;
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}
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break;
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default:
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break;
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}
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}
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uint32_t amd756_smb_ioport_readb(void *opaque, uint32_t addr)
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{
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AMD756SMBus *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch (addr) {
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case SMB_GLOBAL_STATUS:
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val = s->smb_stat;
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break;
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case SMB_GLOBAL_ENABLE:
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// s->smb_index = 0;
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val = s->smb_ctl & 0x1f;
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break;
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case SMB_HOST_COMMAND:
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val = s->smb_cmd;
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break;
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case SMB_HOST_ADDRESS:
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val = s->smb_addr;
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break;
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case SMB_HOST_DATA:
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val = s->smb_data0;
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break;
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case SMB_HOST_DATA + 1:
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val = s->smb_data1;
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break;
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case SMB_HOST_BLOCK_DATA:
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val = s->smb_data[s->smb_index++];
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if (s->smb_index > 31) {
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s->smb_index = 0;
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}
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break;
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default:
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val = 0;
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break;
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}
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SMBUS_DPRINTF("SMB readb port=0x%04x val=0x%02x\n", addr, val);
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return val;
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}
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void amd756_smbus_init(DeviceState *parent, AMD756SMBus *smb, qemu_irq irq)
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{
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smb->smbus = i2c_init_bus(parent, "i2c");
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smb->smb_stat = 0;
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smb->irq = irq;
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}
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