mirror of https://github.com/xemu-project/xemu.git
c4db48cc24
This commit allows program to write textra trigger CSR for type 2, 3, 6 triggers. In this preliminary patch, the textra.MHVALUE and the textra.MHSELECT fields are allowed to be configured. Other fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240826024657.262553-2-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| alpha | ||
| arm | ||
| avr | ||
| hexagon | ||
| hppa | ||
| i386 | ||
| loongarch | ||
| m68k | ||
| microblaze | ||
| mips | ||
| openrisc | ||
| ppc | ||
| riscv | ||
| rx | ||
| s390x | ||
| sh4 | ||
| sparc | ||
| tricore | ||
| xtensa | ||
| Kconfig | ||
| meson.build | ||