xemu/target
Xin Li c1acad9f72 target/i386: add support for FRED in CPUID enumeration
FRED, i.e., the Intel flexible return and event delivery architecture,
defines simple new transitions that change privilege level (ring
transitions).

The new transitions defined by the FRED architecture are FRED event
delivery and, for returning from events, two FRED return instructions.
FRED event delivery can effect a transition from ring 3 to ring 0, but
it is used also to deliver events incident to ring 0.  One FRED
instruction (ERETU) effects a return from ring 0 to ring 3, while the
other (ERETS) returns while remaining in ring 0.  Collectively, FRED
event delivery and the FRED return instructions are FRED transitions.

In addition to these transitions, the FRED architecture defines a new
instruction (LKGS) for managing the state of the GS segment register.
The LKGS instruction can be used by 64-bit operating systems that do
not use the new FRED transitions.

WRMSRNS is an instruction that behaves exactly like WRMSR, with the
only difference being that it is not a serializing instruction by
default.  Under certain conditions, WRMSRNS may replace WRMSR to improve
performance.  FRED uses it to switch RSP0 in a faster manner.

Search for the latest FRED spec in most search engines with this search
pattern:

  site:intel.com FRED (flexible return and event delivery) specification

The CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[17] enumerates FRED, and
the CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[18] enumerates LKGS, and
the CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[19] enumerates WRMSRNS.

Add CPUID definitions for FRED/LKGS/WRMSRNS, and expose them to KVM guests.

Because FRED relies on LKGS and WRMSRNS, add that to feature dependency
map.

Tested-by: Shan Kang <shan.kang@intel.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Message-ID: <20231109072012.8078-2-xin3.li@intel.com>
[Fix order of dependencies, add dependencies from LM to FRED. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-08 10:33:38 +02:00
..
alpha accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
arm target/arm: Replace sprintf() by snprintf() 2024-06-04 10:02:39 +02:00
avr target/avr: Use translator_lduw 2024-05-15 08:55:19 +02:00
cris target/cris: Use cris_fetch in translate_v10.c.inc 2024-05-15 08:55:19 +02:00
hexagon target/hexagon: Use translator_ldl in pkt_crosses_page 2024-05-15 08:55:19 +02:00
hppa target/hppa: 2024-05-15 11:46:58 +02:00
i386 target/i386: add support for FRED in CPUID enumeration 2024-06-08 10:33:38 +02:00
loongarch target/loongarch: Add loongarch vector property unconditionally 2024-05-23 09:30:41 +08:00
m68k accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
microblaze target/microblaze: Use translator_ldl 2024-05-15 08:55:19 +02:00
mips target/mips: Remove unused 'hw/misc/mips_itu.h' header 2024-06-04 10:02:39 +02:00
openrisc accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
ppc target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() 2024-05-24 09:43:14 +10:00
riscv Misc HW & accelerators patch queue 2024-06-04 14:53:05 -05:00
rx target/rx: Use translator_ld* 2024-05-15 08:55:19 +02:00
s390x target/s390x: Adjust check of noreturn in translate_one 2024-05-29 12:41:56 +02:00
sh4 accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
sparc accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
tricore accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
xtensa target/xtensa: Use translator_ldub in xtensa_insn_len 2024-05-15 08:55:19 +02:00
Kconfig meson: make target endianneess available to Kconfig 2024-05-03 15:47:47 +02:00
meson.build exec: Expose 'target_page.h' API to user emulation 2024-04-26 15:28:11 +02:00