Philipp Tomsich 90f9e35b78 target/riscv: fix inverted checks for ext_zb[abcs] ... While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS] inadvertently became inverted and slipped through the initial testing (which used RV64GC_XVentanaCondOps as a target). This fixes the regression. Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs. Fixes: f2a32bec8f ("target/riscv: access cfg structure through DisasContext") Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-03-03 13:14:50 +10:00
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trans_privileged.c.inc	target/riscv: Sign extend pc for different XLEN	2022-01-21 15:52:57 +10:00
trans_rva.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvb.c.inc	target/riscv: fix inverted checks for ext_zb[abcs]	2022-03-03 13:14:50 +10:00
trans_rvd.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvf.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00
trans_rvm.c.inc	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
trans_rvv.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00
trans_rvzfh.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00
trans_svinval.c.inc	target/riscv: add support for svinval extension	2022-02-16 12:25:52 +10:00
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00