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Philippe Mathieu-Daudé ba7b6f025b target/mips: Fix Loongson-3A4000 MSAIR config register 
When using the Loongson-3A4000 CPU, the MSAIR is returned with a
zero value (because unimplemented). Checking on real hardware,
this value appears incorrect:

  $ cat /proc/cpuinfo
  system type     : generic-loongson-machine
  machine         : loongson,generic
  cpu model       : Loongson-3 V0.4  FPU V0.1
  model name      : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
  isa             : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
  ASEs implemented        : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2
  ...

Checking the CFCMSA opcode result with gdb we get 0x60140:

  Breakpoint 1, 0x00000001200037c4 in main ()
  1: x/i $pc
  => 0x1200037c4 <main+52>:  cfcmsa       v0,msa_ir
  (gdb) si
  0x00000001200037c8 in main ()
  (gdb) i r v0
  v0: 0x60140

MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12,
so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000
CPU model added in commit af868995e1.

Cc: Huacai Chen <chenhuacai@kernel.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211026180920.1085516-1-f4bug@amsat.org>
 		2021-11-02 14:32:32 +01:00
..
alpha target/alpha: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
arm target/arm: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
avr target/avr: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
cris target/cris: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
hexagon Hexagon (target/hexagon) put writes to USR into temp until commit 2021-10-28 22:22:49 -05:00
hppa target/hppa: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
i386 target/i386: Remove core-capability in Snowridge CPU model 2021-10-29 15:02:30 -04:00
m68k target/m68k: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
microblaze target/microblaze: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
mips target/mips: Fix Loongson-3A4000 MSAIR config register 2021-11-02 14:32:32 +01:00
nios2 disas/nios2: Simplify endianess conversion 2021-10-22 18:07:30 +02:00
openrisc target/openrisc: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
ppc host-utils: add 128-bit quotient support to divu128/divs128 2021-10-27 17:10:00 -07:00
riscv target/riscv: change the api for RVF/RVD fmin/fmax 2021-10-29 16:56:12 +10:00
rx target/rx: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
s390x target/s390x: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
sh4 target/sh4: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
sparc target/sparc: Use cpu_*_mmu instead of helper_*_mmu 2021-10-13 08:45:13 -07:00
tricore target/tricore: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
xtensa target/xtensa: Drop check for singlestep_enabled 2021-10-15 16:39:15 -07:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00