xemu/target/i386
Paolo Bonzini b3e22b2318 target/i386: add core of new i386 decoder
The new decoder is based on three principles:

- use mostly table-driven decoding, using tables derived as much as possible
  from the Intel manual.  Centralizing the decode the operands makes it
  more homogeneous, for example all immediates are signed.  All modrm
  handling is in one function, and can be shared between SSE and ALU
  instructions (including XMM<->GPR instructions).  The SSE/AVX decoder
  will also not have duplicated code between the 0F, 0F38 and 0F3A tables.

- keep the code as "non-branchy" as possible.  Generally, the code for
  the new decoder is more verbose, but the control flow is simpler.
  Conditionals are not nested and have small bodies.  All instruction
  groups are resolved even before operands are decoded, and code
  generation is separated as much as possible within small functions
  that only handle one instruction each.

- keep address generation and (for ALU operands) memory loads and writeback
  as much in common code as possible.  All ALU operations for example
  are implemented as T0=f(T0,T1).  For non-ALU instructions,
  read-modify-write memory operations are rare, but registers do not
  have TCGv equivalents: therefore, the common logic sets up pointer
  temporaries with the operands, while load and writeback are handled
  by gvec or by helpers.

These principles make future code review and extensibility simpler, at
the cost of having a relatively large amount of code in the form of this
patch.  Even EVEX should not be _too_ hard to implement (it's just a crazy
large amount of possibilities).

This patch introduces the main decoder flow, and integrates the old
decoder with the new one.  The old decoder takes care of parsing
prefixes and then optionally drops to the new one.  The changes to the
old decoder are minimal and allow it to be replaced incrementally with
the new one.

There is a debugging mechanism through a "LIMIT" environment variable.
In user-mode emulation, the variable is the number of instructions
decoded by the new decoder before permanently switching to the old one.
In system emulation, the variable is the highest opcode that is decoded
by the new decoder (this is less friendly, but it's the best that can
be done without requiring deterministic execution).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-18 13:58:04 +02:00
..
hax Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
hvf hvf: Enable RDTSCP support 2022-07-13 00:05:39 +02:00
kvm hyperv: fix SynIC SINT assertion failure on guest reset 2022-10-18 13:58:04 +02:00
nvmm Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
tcg target/i386: add core of new i386 decoder 2022-10-18 13:58:04 +02:00
whpx Drop superfluous conditionals around g_free() 2022-10-04 00:10:11 +02:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
arch_memory_mapping.c exec,dump,i386,ppc,s390x: don't include exec/cpu-all.h explicitly 2017-09-19 18:21:33 +02:00
cpu-dump.c monitor: Trim some trailing space from human-readable output 2021-10-31 21:05:40 +01:00
cpu-internal.h i386: split off sysemu part of cpu.c 2021-05-10 15:41:52 -04:00
cpu-param.h target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX 2022-10-18 13:58:04 +02:00
cpu-qom.h target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro 2022-03-06 22:23:09 +01:00
cpu-sysemu.c Fix 'writeable' typos 2022-06-08 19:38:47 +01:00
cpu.c target/i386: Use device_cold_reset() to reset the APIC 2022-10-18 13:58:04 +02:00
cpu.h target/i386: Define XMMReg and access macros, align ZMM registers 2022-10-18 13:58:04 +02:00
gdbstub.c target/i386: fix byte swap issue with XMM register access 2022-04-20 16:04:20 +01:00
helper.c monitor: expose monitor_puts to rest of code 2022-10-06 11:53:40 +01:00
helper.h target/i386: Truncate values for lcall_real to i32 2022-10-11 09:36:01 +02:00
host-cpu.c i386: do not call cpudef-only models functions for max, host, base 2021-07-23 15:47:13 +02:00
host-cpu.h accel-cpu: make cpu_realizefn return a bool 2021-05-10 15:41:50 -04:00
machine.c i386: kvm: extend kvm_{get, put}_vcpu_events to support pending triple fault 2022-10-10 09:23:16 +02:00
meson.build target/i386/sev: Remove stubs by using code elision 2021-10-13 10:47:49 +02:00
monitor.c monitor: remove 'info ioapic' HMP command 2021-11-02 15:55:13 +00:00
ops_sse.h target/i386: fix INSERTQ implementation 2022-09-19 15:16:00 +02:00
ops_sse_header.h target/i386: fix INSERTQ implementation 2022-09-19 15:16:00 +02:00
sev-sysemu-stub.c monitor: Reduce hmp_info_sev() declaration 2021-10-13 10:47:49 +02:00
sev.c qapi, target/i386/sev: Add cpu0-id to query-sev-capabilities 2022-04-06 10:50:37 +02:00
sev.h Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
shift_helper_template.h x86 tcg cpus: Fix Lesser GPL version number 2020-11-15 16:41:42 +01:00
svm.h target/i386: Added vVMLOAD and vVMSAVE feature 2021-09-13 13:56:26 +02:00
trace-events * Update the references to some doc files (use *.rst instead of *.txt) 2021-06-02 17:08:11 +01:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
xsave_helper.c x86: add support for KVM_CAP_XSAVE2 and AMX state migration 2022-03-15 11:50:50 +01:00