Richard Henderson db23e5d981 target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl ... Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-22 07:47:51 +10:00
..
Kconfig	semihosting: Move hw/semihosting/ -> semihosting/	2021-03-10 15:34:12 +00:00
arm-compat-semi.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
common-semi.h	semihosting: Move hw/semihosting/ -> semihosting/	2021-03-10 15:34:12 +00:00
config.c	Do not include sysemu/sysemu.h if it's not really necessary	2021-05-02 17:24:50 +02:00
console.c	Do not include cpu.h if it's not really necessary	2021-05-02 17:24:51 +02:00
meson.build	semihosting: Move hw/semihosting/ -> semihosting/	2021-03-10 15:34:12 +00:00