Alistair Francis a06fded82e hw/riscv: opentitan: Expose the resetvec as a SoC property ... On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set the resetvec from the command line with something like this: -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400 This way as the next stage changes we can update the resetvec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-09-27 07:04:38 +10:00
..
boot.h	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
boot_opensbi.h	Clean up header guards that don't match their file name	2022-05-11 16:49:06 +02:00
microchip_pfsoc.h	hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals	2022-09-07 09:18:33 +02:00
numa.h	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.h	hw/riscv: opentitan: Expose the resetvec as a SoC property	2022-09-27 07:04:38 +10:00
riscv_hart.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
shakti_c.h	Clean up header guards that don't match their file name	2022-05-11 16:49:06 +02:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	sifive_e: Rename memmap enum constants	2020-09-18 13:49:48 -04:00
sifive_u.h	hw/riscv: sifive_u: Use the PLIC config helper function	2021-10-28 14:39:23 +10:00
spike.h	hw/riscv: spike: Allow using binary firmware as bios	2022-01-21 15:52:56 +10:00
virt.h	hw/riscv: virt: fix the plic's address cells	2022-09-07 09:18:33 +02:00