Anup Patel 6c60757eb6 sifive_u: Set 'clock-frequency' DT property for SiFive UART ... The 'clock-frequency' DT property is required by U-Boot to compute the divider value. This patch sets the 'clock-frequency' DT property of the SiFive UART device tree node (similar to virt machine). Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-12-20 12:03:26 -08:00
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Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
riscv_hart.c	riscv_hart: Fix crash when introspecting the device	2018-07-19 09:05:48 -07:00
riscv_htif.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
sifive_clint.c	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
sifive_e.c	Drop "qemu:" prefix from error_report() arguments	2018-09-24 17:13:07 +02:00
sifive_plic.c	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
sifive_prci.c	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.c	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.c	sifive_u: Set 'clock-frequency' DT property for SiFive UART	2018-12-20 12:03:26 -08:00
sifive_uart.c	SiFive RISC-V UART Device	2018-03-07 08:30:28 +13:00
spike.c	riscv: spike: Fix memory leak in the board init	2018-11-08 08:41:06 -08:00
virt.c	hw/riscv/virt: Connect the gpex PCIe	2018-12-20 11:45:20 -08:00