Jerry Zhang Jian 15b8ddb18a target/riscv: zvbb implies zvkb ... According to RISC-V crypto spec, Zvkb extension is a subset of the Zvbb extension [1]. 1: 1769c2609b/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240528130349.20193-1-jerry.zhangjian@sifive.com> [ Changes by AF: - Tidy up commit message - Rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-06-26 22:30:52 +10:00
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meson.build	target/riscv: introduce TCG AccelCPUClass	2023-10-12 11:55:21 +10:00
tcg-cpu.c	target/riscv: zvbb implies zvkb	2024-06-26 22:30:52 +10:00
tcg-cpu.h	target/riscv: Implement dynamic establishment of custom decoder	2024-06-03 11:12:12 +10:00