xemu/target
Huang Tao 8c8a7cd647 target/riscv: Implement dynamic establishment of custom decoder
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-03 11:12:12 +10:00
..
alpha accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
arm target/arm: Implement FEAT WFxT and enable for '-cpu max' 2024-05-30 16:35:17 +01:00
avr target/avr: Use translator_lduw 2024-05-15 08:55:19 +02:00
cris target/cris: Use cris_fetch in translate_v10.c.inc 2024-05-15 08:55:19 +02:00
hexagon target/hexagon: Use translator_ldl in pkt_crosses_page 2024-05-15 08:55:19 +02:00
hppa target/hppa: 2024-05-15 11:46:58 +02:00
i386 accel/tcg: Make TCGCPUOps::cpu_exec_halt return bool for whether to halt 2024-05-30 16:13:48 +01:00
loongarch target/loongarch: Add loongarch vector property unconditionally 2024-05-23 09:30:41 +08:00
m68k accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
microblaze target/microblaze: Use translator_ldl 2024-05-15 08:55:19 +02:00
mips accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
openrisc accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
ppc target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() 2024-05-24 09:43:14 +10:00
riscv target/riscv: Implement dynamic establishment of custom decoder 2024-06-03 11:12:12 +10:00
rx target/rx: Use translator_ld* 2024-05-15 08:55:19 +02:00
s390x target/s390x: Adjust check of noreturn in translate_one 2024-05-29 12:41:56 +02:00
sh4 accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
sparc accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
tricore accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
xtensa target/xtensa: Use translator_ldub in xtensa_insn_len 2024-05-15 08:55:19 +02:00
Kconfig meson: make target endianneess available to Kconfig 2024-05-03 15:47:47 +02:00
meson.build exec: Expose 'target_page.h' API to user emulation 2024-04-26 15:28:11 +02:00