xemu/target
Peter Maydell 872d20343d target/arm: Honour MDCR_EL2.HPMD in Secure EL2
The logic in pmu_counter_enabled() for handling the 'prohibit event
counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way
that assumes that EL2 is never Secure.  This used to be true, but the
architecture now permits Secure EL2, and QEMU can emulate this.

Refactor the prohibit logic so that we effectively OR together
the various prohibit bits when they apply, rather than trying to
construct an if-else ladder where any particular state of the CPU
ends up in exactly one branch of the ladder.

This fixes the Secure EL2 case and also is a better structure for
adding the PMUv8.5 bits MDCR_EL2.HCCD and MDCR_EL3.SCCD.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-6-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-14 11:19:40 +01:00
..
alpha accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
arm target/arm: Honour MDCR_EL2.HPMD in Secure EL2 2022-09-14 11:19:40 +01:00
avr accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
cris accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
hexagon accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
hppa accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
i386 target/i386: Make translator stop before the end of a page 2022-09-06 08:04:26 +01:00
loongarch accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
m68k accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
microblaze accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
mips accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
nios2 accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
openrisc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
ppc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
riscv target/riscv: Update the privilege field for sscofpmf CSRs 2022-09-07 09:19:15 +02:00
rx accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
s390x target/s390x: Make translator stop before the end of a page 2022-09-06 08:04:26 +01:00
sh4 accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
sparc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
tricore accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
xtensa accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00