xemu/include
Stefan Hajnoczi 85f1051248 target-arm queue:
* enable FEAT_RNG on Neoverse-N2
  * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
  * Fix SME FMOPA (16-bit), BFMOPA
  * hw/core/machine: Constify MachineClass::valid_cpu_types[]
  * stm32f* machines: Report error when user asks for wrong CPU type
  * hw/arm/fsl-imx: Do not ignore Error argument
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVchLYZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kHMD/47tKxzrsXc6+V9esRQGi2H
 1hAgLBwglEdxLXokF+Di41sh/fvK7wYVXO/hiWlq+9h3kG3D/u1N5r1TdMPMUb9j
 4Sg3rOejn7nzkxVZ6MZ/K/1j84C9bfrt4sboVHZVRvWuvbiyuTuivEr4IqLYO4x3
 AIwhFMQ5gbNrmClZh/DBxj0keO13cp63Fg2JSSICdi+1Dw9rRXTyhJloMu1omeqc
 k/BXzjSeNXpLSMyGWBR3uaPcJBaGC1xnz3Z1V7fUY1EYD2Cu1oo5lEZ9aNO5t30d
 XW/qVGLa3b1Cb7WuEO247RnU3N2oZotozjFtdj/8IQoYWspM9RHyipEimUlegVdO
 3fpu8QGsN1ljNiwjdk0i6OwS7SGxcPtteFOaqEf/Yogj4EOKTn/Rx5TT4vJ5DhmI
 2w/9J15JWDIE1paNwecuFWbxCOOzSsOtSxzuyLSZDU3GlNfJ4zoF6YboROLYfejy
 NXZABFhGd/0ykX7r0VY1GGYXUQ+akv6q+VDmVZCP9gMiRUiqmFPwMLMLlcuHb8G5
 8UztN5SvOG2EYXj28Zx0BnGCNiGdI15rWMb0veqAtbnn3yEdltW3O475BAhZ0PB7
 OVpLWnXwmWURm/BGlwb1PH5s3kgWgzOebcBgcnCftwFQ8EedQAQDA5FmT+nK5SfV
 VoOf89PngTubU6B3BOfeBw==
 =thIa
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20231121' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * enable FEAT_RNG on Neoverse-N2
 * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
 * Fix SME FMOPA (16-bit), BFMOPA
 * hw/core/machine: Constify MachineClass::valid_cpu_types[]
 * stm32f* machines: Report error when user asks for wrong CPU type
 * hw/arm/fsl-imx: Do not ignore Error argument

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVchLYZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kHMD/47tKxzrsXc6+V9esRQGi2H
# 1hAgLBwglEdxLXokF+Di41sh/fvK7wYVXO/hiWlq+9h3kG3D/u1N5r1TdMPMUb9j
# 4Sg3rOejn7nzkxVZ6MZ/K/1j84C9bfrt4sboVHZVRvWuvbiyuTuivEr4IqLYO4x3
# AIwhFMQ5gbNrmClZh/DBxj0keO13cp63Fg2JSSICdi+1Dw9rRXTyhJloMu1omeqc
# k/BXzjSeNXpLSMyGWBR3uaPcJBaGC1xnz3Z1V7fUY1EYD2Cu1oo5lEZ9aNO5t30d
# XW/qVGLa3b1Cb7WuEO247RnU3N2oZotozjFtdj/8IQoYWspM9RHyipEimUlegVdO
# 3fpu8QGsN1ljNiwjdk0i6OwS7SGxcPtteFOaqEf/Yogj4EOKTn/Rx5TT4vJ5DhmI
# 2w/9J15JWDIE1paNwecuFWbxCOOzSsOtSxzuyLSZDU3GlNfJ4zoF6YboROLYfejy
# NXZABFhGd/0ykX7r0VY1GGYXUQ+akv6q+VDmVZCP9gMiRUiqmFPwMLMLlcuHb8G5
# 8UztN5SvOG2EYXj28Zx0BnGCNiGdI15rWMb0veqAtbnn3yEdltW3O475BAhZ0PB7
# OVpLWnXwmWURm/BGlwb1PH5s3kgWgzOebcBgcnCftwFQ8EedQAQDA5FmT+nK5SfV
# VoOf89PngTubU6B3BOfeBw==
# =thIa
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 21 Nov 2023 05:21:42 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20231121' of https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/arm/fsl-imx: Do not ignore Error argument
  hw/arm/stm32f100: Report error when incorrect CPU is used
  hw/arm/stm32f205: Report error when incorrect CPU is used
  hw/arm/stm32f405: Report error when incorrect CPU is used
  hw/core/machine: Constify MachineClass::valid_cpu_types[]
  target/arm: Fix SME FMOPA (16-bit), BFMOPA
  hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
  target/arm: enable FEAT_RNG on Neoverse-N2

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-21 06:24:53 -05:00
..
authz Prefer 'on' | 'off' over 'yes' | 'no' for bool options 2021-01-29 17:07:53 +00:00
block include/block/ufs.h: spelling fix: setted 2023-11-15 12:06:04 +03:00
chardev include/: spelling fixes 2023-09-08 13:08:52 +03:00
crypto crypto: Add generic 64-bit carry-less multiply routine 2023-09-15 13:57:00 +00:00
disas disas: Change type of disassemble_info.target_info to pointer 2023-06-13 17:25:47 +10:00
exec accel/tcg: Remove CF_LAST_IO 2023-11-14 10:40:54 -08:00
fpu fpu: Add conversions between bfloat16 and [u]int8 2023-09-16 14:57:15 +00:00
gdbstub gdbstub: replace exit calls with proper shutdown for softmmu 2023-10-12 12:36:37 +10:00
hw hw/arm/stm32f100: Report error when incorrect CPU is used 2023-11-20 15:30:59 +00:00
io io: follow coroutine AioContext in qio_channel_yield() 2023-09-07 20:32:11 -05:00
libdecnumber Replace config-time define HOST_WORDS_BIGENDIAN 2022-04-06 10:50:37 +02:00
migration migration: per-mode blockers 2023-11-01 16:13:59 +01:00
monitor monitor: add more *_locked() functions 2023-05-25 10:18:33 +02:00
net net: Update MemReentrancyGuard for NIC 2023-11-21 15:42:34 +08:00
qapi qobject atomics osdep: Make a few macros more hygienic 2023-09-29 08:13:57 +02:00
qemu host/include/generic/host/atomic128: Fix compilation problem with Clang 17 2023-11-13 11:35:47 +01:00
qom qom: Add object_property_set_default_list() 2023-11-10 18:19:14 +01:00
scsi hw/ufs: Support for UFS logical unit 2023-09-07 14:01:29 -04:00
semihosting * util/log: re-allow switching away from stderr log file 2023-10-09 10:11:18 -04:00
standard-headers linux-headers: Update to Linux v6.6-rc1 2023-09-12 11:34:56 +02:00
sysemu dump: Add arch cleanup function 2023-11-14 10:42:32 +01:00
tcg tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} 2023-11-06 08:27:21 -08:00
ui virtio-gpu: replace PIXMAN for region/rect test 2023-11-07 14:04:25 +04:00
user bulk: Do not declare function prototypes using 'extern' keyword 2023-08-31 19:47:43 +02:00
elf.h util: spelling fixes 2023-08-31 19:47:43 +02:00
glib-compat.h compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
qemu-io.h Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
qemu-main.h ui/cocoa: Run qemu_init in the main thread 2022-09-23 14:36:33 +02:00