xemu/target
Paolo Bonzini 7170a17ec3 target/i386: reimplement 0x0f 0x10-0x17, add AVX
These are mostly moves, and yet are a total pain.  The main issue
is that:

1) some instructions are selected by mod==11 (register operand)
vs. mod=00/01/10 (memory operand)

2) stores to memory are two-operand operations, while the 3-register
and load-from-memory versions operate on the entire contents of the
destination; this makes it easier to separate the gen_* function for
the store case

3) it's inefficient to load into xmm_T0 only to move the value out
again, so the gen_* function for the load case is separated too

The manual also has various mistakes in the operands here, for example
the store case of MOVHPS operates on a 128-bit source (albeit discarding
the bottom 64 bits) and therefore should be Mq,Vdq rather than Mq,Vq.
Likewise for the destination and source of MOVHLPS.

VUNPCK?PS and VUNPCK?PD are the same as VUNPCK?DQ and VUNPCK?QDQ,
but encoded as prefixes rather than separate operands.  The helpers
can be reused however.

For MOVSLDUP, MOVSHDUP and MOVDDUP I chose to reimplement them as
helpers.  I named the helper for MOVDDUP "movdldup" in preparation
for possible future introduction of MOVDHDUP and to clarify the
similarity with MOVSLDUP.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-18 13:58:05 +02:00
..
alpha hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
arm * scsi-disk: support setting CD-ROM block size via device options 2022-10-13 13:55:03 -04:00
avr accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
cris hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
hexagon Make store handling faster and more robust 2022-10-05 10:17:32 -04:00
hppa accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
i386 target/i386: reimplement 0x0f 0x10-0x17, add AVX 2022-10-18 13:58:05 +02:00
loongarch accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
m68k hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
microblaze accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
mips kvm: allow target-specific accelerator properties 2022-10-10 09:23:16 +02:00
nios2 hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
openrisc accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
ppc * scsi-disk: support setting CD-ROM block size via device options 2022-10-13 13:55:03 -04:00
riscv * scsi-disk: support setting CD-ROM block size via device options 2022-10-13 13:55:03 -04:00
rx accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
s390x * scsi-disk: support setting CD-ROM block size via device options 2022-10-13 13:55:03 -04:00
sh4 target/sh4: Fix TB_FLAG_UNALIGN 2022-10-04 12:33:05 -07:00
sparc accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
tricore accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
xtensa hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00