mirror of https://github.com/xemu-project/xemu.git
257 lines
7.1 KiB
C
257 lines
7.1 KiB
C
/*
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* DSP56300 emulator
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*
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* Copyright (c) 2015 espes
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*
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* Adapted from Hatari DSP M56001 emulation
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* (C) 2003-2008 ARAnyM developer team
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* Adaption to Hatari (C) 2008 by Thomas Huth
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef DSP_CPU_H
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#define DSP_CPU_H
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#define DSP_OMR_MA 0x00
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#define DSP_OMR_MB 0x01
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#define DSP_OMR_DE 0x02
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#define DSP_OMR_SD 0x06
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#define DSP_OMR_EA 0x07
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#define DSP_SR_C 0x00
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#define DSP_SR_V 0x01
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#define DSP_SR_Z 0x02
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#define DSP_SR_N 0x03
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#define DSP_SR_U 0x04
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#define DSP_SR_E 0x05
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#define DSP_SR_L 0x06
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#define DSP_SR_I0 0x08
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#define DSP_SR_I1 0x09
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#define DSP_SR_S0 0x0a
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#define DSP_SR_S1 0x0b
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#define DSP_SR_T 0x0d
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#define DSP_SR_LF 0x0f
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#define DSP_SP_SE 0x04
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#define DSP_SP_UF 0x05
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/* Registers numbers in dsp.registers[] */
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#define DSP_REG_X0 0x04
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#define DSP_REG_X1 0x05
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#define DSP_REG_Y0 0x06
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#define DSP_REG_Y1 0x07
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#define DSP_REG_A0 0x08
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#define DSP_REG_B0 0x09
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#define DSP_REG_A2 0x0a
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#define DSP_REG_B2 0x0b
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#define DSP_REG_A1 0x0c
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#define DSP_REG_B1 0x0d
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#define DSP_REG_A 0x0e
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#define DSP_REG_B 0x0f
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#define DSP_REG_R0 0x10
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#define DSP_REG_R1 0x11
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#define DSP_REG_R2 0x12
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#define DSP_REG_R3 0x13
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#define DSP_REG_R4 0x14
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#define DSP_REG_R5 0x15
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#define DSP_REG_R6 0x16
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#define DSP_REG_R7 0x17
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#define DSP_REG_N0 0x18
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#define DSP_REG_N1 0x19
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#define DSP_REG_N2 0x1a
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#define DSP_REG_N3 0x1b
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#define DSP_REG_N4 0x1c
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#define DSP_REG_N5 0x1d
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#define DSP_REG_N6 0x1e
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#define DSP_REG_N7 0x1f
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#define DSP_REG_M0 0x20
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#define DSP_REG_M1 0x21
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#define DSP_REG_M2 0x22
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#define DSP_REG_M3 0x23
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#define DSP_REG_M4 0x24
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#define DSP_REG_M5 0x25
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#define DSP_REG_M6 0x26
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#define DSP_REG_M7 0x27
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#define DSP_REG_SR 0x39
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#define DSP_REG_OMR 0x3a
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#define DSP_REG_SP 0x3b
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#define DSP_REG_SSH 0x3c
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#define DSP_REG_SSL 0x3d
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#define DSP_REG_LA 0x3e
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#define DSP_REG_LC 0x3f
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#define DSP_REG_NULL 0x00
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#define DSP_REG_LCSAVE 0x30
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#define DSP_REG_MAX 0x40
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/* Memory spaces for dsp.ram[], dsp.rom[] */
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#define DSP_SPACE_X 0x00
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#define DSP_SPACE_Y 0x01
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#define DSP_SPACE_P 0x02
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#define DSP_XRAM_SIZE 4096
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#define DSP_YRAM_SIZE 2048
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#define DSP_PRAM_SIZE 4096
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#define DSP_MIXBUFFER_BASE 0x001400
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#define DSP_MIXBUFFER_SIZE 1024
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#define DSP_PERIPH_BASE 0xFFFF80
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#define DSP_PERIPH_SIZE 128
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#define DSP_INTERRUPT_NONE 0x0
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#define DSP_INTERRUPT_DISABLED 0x1
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#define DSP_INTERRUPT_LONG 0x2
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#define DSP_INTER_RESET 0x0
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#define DSP_INTER_ILLEGAL 0x1
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#define DSP_INTER_STACK_ERROR 0x2
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#define DSP_INTER_TRACE 0x3
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#define DSP_INTER_SWI 0x4
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#define DSP_INTER_HOST_COMMAND 0x5
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#define DSP_INTER_HOST_RCV_DATA 0x6
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#define DSP_INTER_HOST_TRX_DATA 0x7
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#define DSP_INTER_SSI_RCV_DATA_E 0x8
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#define DSP_INTER_SSI_RCV_DATA 0x9
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#define DSP_INTER_SSI_TRX_DATA_E 0xa
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#define DSP_INTER_SSI_TRX_DATA 0xb
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typedef enum {
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DSP_TRACE_MODE,
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DSP_DISASM_MODE
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} dsp_trace_disasm_t;
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typedef struct dsp_interrupt_s {
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const uint16_t inter;
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const uint16_t vectorAddr;
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const uint16_t periph;
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const char *name;
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} dsp_interrupt_t;
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typedef struct dsp_core_s dsp_core_t;
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struct dsp_core_s {
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/* DSP instruction Cycle counter */
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uint16_t instr_cycle;
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/* Registers */
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uint32_t pc;
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uint32_t registers[DSP_REG_MAX];
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/* stack[0=ssh], stack[1=ssl] */
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uint32_t stack[2][16];
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uint32_t xram[DSP_XRAM_SIZE];
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uint32_t yram[DSP_YRAM_SIZE];
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uint32_t pram[DSP_PRAM_SIZE];
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uint32_t mixbuffer[DSP_MIXBUFFER_SIZE];
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/* peripheral space, x:0xffff80-0xffffff */
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uint32_t periph[DSP_PERIPH_SIZE];
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/* Misc */
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uint32_t loop_rep; /* executing rep ? */
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uint32_t pc_on_rep; /* True if PC is on REP instruction */
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/* Interruptions */
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uint16_t interrupt_state; /* NONE, FAST or LONG interrupt */
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uint16_t interrupt_instr_fetch; /* vector of the current interrupt */
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uint16_t interrupt_save_pc; /* save next pc value before interrupt */
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uint16_t interrupt_counter; /* count number of pending interrupts */
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uint16_t interrupt_ipl_to_raise; /* save the IPL level to save in the SR register */
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uint16_t interrupt_pipeline_count; /* used to prefetch correctly the 2 inter instructions */
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int16_t interrupt_ipl[12]; /* store the current IPL for each interrupt */
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uint16_t interrupt_is_pending[12]; /* store if interrupt is pending for each interrupt */
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/* callbacks */
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uint32_t (*read_peripheral)(dsp_core_t* core, uint32_t address);
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void (*write_peripheral)(dsp_core_t* core, uint32_t address, uint32_t value);
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/* runtime data */
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/* Instructions per second */
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#ifdef DSP_COUNT_IPS
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uint32_t start_time;
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#endif
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uint32_t num_inst;
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/* Length of current instruction */
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uint32_t cur_inst_len; /* =0:jump, >0:increment */
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/* Current instruction */
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uint32_t cur_inst;
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/* DSP is in disasm mode ? */
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/* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
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bool executing_for_disasm;
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char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
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uint32_t disasm_memory_ptr; /* Pointer for memory change in disasm mode */
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bool exception_debugging;
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/* disasm data */
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/* Previous instruction */
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uint32_t disasm_prev_inst_pc;
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bool disasm_is_looping;
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/* Used to display dc instead of unknown instruction for illegal opcodes */
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dsp_trace_disasm_t disasm_mode;
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uint32_t disasm_cur_inst;
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uint16_t disasm_cur_inst_len;
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/* Current instruction */
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char disasm_str_instr[128];
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char disasm_str_instr2[128];
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char disasm_parallelmove_name[64];
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/**********************************
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* Register change
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**********************************/
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uint32_t disasm_registers_save[64];
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#ifdef DSP_DISASM_REG_PC
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uint32_t pc_save;
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#endif
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};
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/* Functions */
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void dsp56k_reset_cpu(dsp_core_t* dsp); /* Set dsp_core to use */
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void dsp56k_execute_instruction(dsp_core_t* dsp); /* Execute 1 instruction */
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uint16_t dsp56k_execute_one_disasm_instruction(dsp_core_t* dsp, FILE *out, uint32_t pc); /* Execute 1 instruction in disasm mode */
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uint32_t dsp56k_read_memory(dsp_core_t* dsp, int space, uint32_t address);
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void dsp56k_write_memory(dsp_core_t* dsp, int space, uint32_t address, uint32_t value);
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/* Interrupt relative functions */
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void dsp56k_add_interrupt(dsp_core_t* dsp, uint16_t inter);
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#endif /* DSP_CPU_H */
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