xemu/target
Daniel Henrique Barboza 68e7c86927 target/riscv: prioritize pmp errors in raise_mmu_exception()
raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-03 11:12:12 +10:00
..
alpha accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
arm target/arm: Implement FEAT WFxT and enable for '-cpu max' 2024-05-30 16:35:17 +01:00
avr target/avr: Use translator_lduw 2024-05-15 08:55:19 +02:00
cris target/cris: Use cris_fetch in translate_v10.c.inc 2024-05-15 08:55:19 +02:00
hexagon target/hexagon: Use translator_ldl in pkt_crosses_page 2024-05-15 08:55:19 +02:00
hppa target/hppa: 2024-05-15 11:46:58 +02:00
i386 accel/tcg: Make TCGCPUOps::cpu_exec_halt return bool for whether to halt 2024-05-30 16:13:48 +01:00
loongarch target/loongarch: Add loongarch vector property unconditionally 2024-05-23 09:30:41 +08:00
m68k accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
microblaze target/microblaze: Use translator_ldl 2024-05-15 08:55:19 +02:00
mips accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
openrisc accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
ppc target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() 2024-05-24 09:43:14 +10:00
riscv target/riscv: prioritize pmp errors in raise_mmu_exception() 2024-06-03 11:12:12 +10:00
rx target/rx: Use translator_ld* 2024-05-15 08:55:19 +02:00
s390x target/s390x: Adjust check of noreturn in translate_one 2024-05-29 12:41:56 +02:00
sh4 accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
sparc accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
tricore accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
xtensa target/xtensa: Use translator_ldub in xtensa_insn_len 2024-05-15 08:55:19 +02:00
Kconfig meson: make target endianneess available to Kconfig 2024-05-03 15:47:47 +02:00
meson.build exec: Expose 'target_page.h' API to user emulation 2024-04-26 15:28:11 +02:00