Jamin Lin 6330be8da4 aspeed/smc: support 64 bits dma dram address ... AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support 64 bits dram address. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>		2024-06-16 21:08:54 +02:00
..
Kconfig	hw/ssi: Implement BCM2835 SPI Controller	2024-02-02 13:51:59 +00:00
aspeed_smc.c	aspeed/smc: support 64 bits dma dram address	2024-06-16 21:08:54 +02:00
bcm2835_spi.c	hw/ssi: Implement BCM2835 SPI Controller	2024-02-02 13:51:59 +00:00
ibex_spi_host.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
imx_spi.c	hw/misc/imx: Replace sprintf() by snprintf()	2024-04-25 12:48:12 +02:00
meson.build	hw/ssi: Implement BCM2835 SPI Controller	2024-02-02 13:51:59 +00:00
mss-spi.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
npcm7xx_fiu.c	hw, target: Add ResetType argument to hold and exit phase methods	2024-04-25 10:21:06 +01:00
npcm_pspi.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
omap_spi.c	hw/arm/omap: Drop useless casts from void * to pointer	2023-01-12 17:15:09 +00:00
pl022.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
sifive_spi.c	hw/ssi/sifive_spi.c: spelling: reigster	2023-01-17 10:02:37 +01:00
ssi.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
stm32f2xx_spi.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
trace-events	aspeed/smc: support 64 bits dma dram address	2024-06-16 21:08:54 +02:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
xilinx_spi.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
xilinx_spips.c	hw/ssi: Constify VMState	2023-12-30 07:38:06 +11:00
xlnx-versal-ospi.c	xlnx-versal-ospi: disable reentrancy detection for iomem_dac	2024-02-27 13:01:41 +00:00