xemu/target
Babu Moger 62a798d4bc target/i386: Add VNMI and automatic IBRS feature bits
Add the following featute bits.

vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the
      guest without using Event Injection mechanism meaning not required to
      track the guest NMI and intercepting the IRET.
      The presence of this feature is indicated via the CPUID function
      0x8000000A_EDX[25].

automatic-ibrs :
      The AMD Zen4 core supports a new feature called Automatic IBRS.
      It is a "set-and-forget" feature that means that, unlike e.g.,
      s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
      resources automatically across CPL transitions.
      The presence of this feature is indicated via the CPUID function
      0x80000021_EAX[8].

The documention for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
   Revision B1 Processors
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
   40332 4.05 Date October 2022

Signed-off-by: Santosh Shukla <santosh.shukla@amd.com>
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Message-Id: <20230504205313.225073-7-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-08 16:35:30 +02:00
..
alpha target/alpha: Use MO_ALIGN where required 2023-05-05 17:05:58 +01:00
arm target/arm: Add compile time asserts to load/store_cpu_field macros 2023-05-02 15:47:41 +01:00
avr target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* 2023-05-05 17:05:28 +01:00
cris target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_* 2023-05-05 17:05:28 +01:00
hexagon target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* 2023-05-05 17:05:28 +01:00
hppa target/hppa: Use MO_ALIGN for system UNALIGN() 2023-05-05 17:05:58 +01:00
i386 target/i386: Add VNMI and automatic IBRS feature bits 2023-05-08 16:35:30 +02:00
loongarch target/loongarch: CPUCFG support LSX 2023-05-06 11:19:50 +08:00
m68k target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_* 2023-05-05 17:05:28 +01:00
microblaze target/microblaze: Remove `NB_MMU_MODES` define 2023-03-13 06:44:37 -07:00
mips target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_* 2023-05-05 17:05:28 +01:00
nios2 target/nios2: Remove `NB_MMU_MODES` define 2023-03-13 06:44:37 -07:00
openrisc target/openrisc: Remove `NB_MMU_MODES` define 2023-03-13 06:44:37 -07:00
ppc tcg: ppc64: Fix mask generation for vextractdm 2023-05-05 12:34:22 -03:00
riscv target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
rx target/rx: Avoid tcg_const_i32 2023-03-13 06:44:37 -07:00
s390x target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* 2023-05-05 17:05:28 +01:00
sh4 target/sh4: Honor QEMU_LOG_FILENAME with QEMU_LOG=cpu 2023-03-16 10:31:25 +01:00
sparc target/sparc: Use cpu_ld*_code_mmu 2023-05-05 17:09:47 +01:00
tricore target/tricore: Use min/max for saturate 2023-03-13 07:03:39 -07:00
xtensa target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_* 2023-05-05 17:05:29 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00