Bin Meng 623d53cb01 hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned ... Currently the firmware dynamic info (fw_dyn) is put right after the reset vector, which is not 8-byte aligned on RV64. OpenSBI fw_dynamic uses ld to read contents from 'struct fw_dynamic_info', which expects fw_dyn to be on the 8-byte boundary, otherwise the misaligned load exception may happen. Fortunately this does not cause any issue on QEMU, as QEMU does support misaligned load. RV32 does not have any issue as it is 4-byte aligned already. Change to make sure it is 8-byte aligned which works for both RV32 and RV64. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-07-15 08:56:00 +10:00
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Kconfig	hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine	2021-05-11 20:02:06 +10:00
boot.c	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
meson.build	riscv: Add initial support for Shakti C machine	2021-05-11 20:01:38 +10:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: Support direct kernel boot	2021-06-08 09:59:42 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer	2021-06-24 05:00:13 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: Connect Shakti UART to Shakti platform	2021-05-11 20:02:06 +10:00
sifive_e.c	hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]	2021-05-11 20:01:10 +10:00
sifive_u.c	hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned	2021-07-15 08:56:00 +10:00
spike.c	hw/riscv: Use macros for BIOS image names	2021-06-08 09:59:42 +10:00
virt.c	hw/riscv: Use macros for BIOS image names	2021-06-08 09:59:42 +10:00