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xemu/target/riscv
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Weiwei Li 61a33ea95a target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version 
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv version to make them invisible to user
if the specified priv version is lower than their minimal priv version.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2023-06-13 16:59:01 +10:00
..
insn_trans accel/tcg: Introduce translator_io_start 2023-06-05 12:04:29 -07:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu-param.h target/riscv: Remove `NB_MMU_MODES` define 2023-03-13 06:44:37 -07:00
cpu-qom.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu.c target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version 2023-06-13 16:59:01 +10:00
cpu.h target/riscv: add PRIV_VERSION_LATEST 2023-06-13 16:56:12 +10:00
cpu_bits.h riscv: Make sure an exception is raised if a pte is malformed 2023-05-05 10:49:50 +10:00
cpu_helper.c tcg: Split out tcg/oversized-guest.h 2023-06-05 12:04:28 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
crypto_helper.c target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
csr.c target/riscv: Restore the predicate() NULL check behavior 2023-05-05 10:49:50 +10:00
debug.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h target/riscv: Handle HLV, HSV via helpers 2023-05-05 10:49:50 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder 2023-03-05 11:49:43 -08:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Introduce mmuidx_2stage 2023-05-05 10:49:50 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c target/riscv: fix SBI getchar handler for KVM 2023-02-07 08:19:23 +10:00
kvm_riscv.h target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
m128_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
machine.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
meson.build target/riscv: add query-cpy-definitions support 2023-05-05 10:49:50 +10:00
monitor.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
op_helper.c target/riscv: Check SUM in the correct register 2023-05-05 10:49:50 +10:00
pmp.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmp.h target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
pmu.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
riscv-qmp-cmds.c target/riscv: add TYPE_RISCV_DYNAMIC_CPU 2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c accel/tcg: Introduce translator_io_start 2023-06-05 12:04:29 -07:00
vector_helper.c target/riscv/vector_helper.c: skip set tail when vta is zero 2023-06-13 16:35:02 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00