mirror of https://github.com/xemu-project/xemu.git
83ad95957c
The current PL031 RTCICR register implementation always clears the IRQ pending status on a register write, regardless of the value the guest writes. To justify that behavior, it references the ARM926EJ-S Development Chip Reference Manual (DDI0287B) and indicates that said document states that any write clears the internal IRQ state. It is indeed true that in section 11.1 this document says: "The interrupt is cleared by writing any data value to the interrupt clear register RTCICR". However, later in section 11.2.2 it contradicts itself by saying: "Writing 1 to bit 0 of RTCICR clears the RTCINTR flag." The latter statement matches the PL031 TRM (DDI0224C), which says: "Writing 1 to bit position 0 clears the corresponding interrupt. Writing 0 has no effect." Let's assume that the self-contradictory DDI0287B is in error, and follow the reference manual for the device itself, by making the register write-one-to-clear. Reported-by: Hendrik Borghorst <hborghor@amazon.de> Signed-off-by: Alexander Graf <graf@amazon.com> Message-id: 20191104115228.30745-1-graf@amazon.com [PMM: updated commit message to note that DDI0287B says two conflicting things] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| Kconfig | ||
| Makefile.objs | ||
| aspeed_rtc.c | ||
| ds1338.c | ||
| exynos4210_rtc.c | ||
| m41t80.c | ||
| m48t59-internal.h | ||
| m48t59-isa.c | ||
| m48t59.c | ||
| mc146818rtc.c | ||
| pl031.c | ||
| sun4v-rtc.c | ||
| trace-events | ||
| twl92230.c | ||
| xlnx-zynqmp-rtc.c | ||