Edgar E. Iglesias 36388314fe mips: Correct MIPS interrupt glue logic for icount ... When hw interrupt pending bits in CP0_Cause are set, the CPU should see the hw interrupt line as active. The CPU may or may not take the interrupt based on internal state (global irq mask etc) but the glue logic shouldn't care. This fixes MIPS external hw interrupts in combination with -icount. Signed-off-by: Edgar E. Iglesias <edgar@axis.com>		2010-07-24 13:40:05 +02:00
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TODO	target-mips: add copyright notice for mips16 work	2009-12-13 20:20:20 +01:00
cpu.h	mips: Correct MIPS interrupt glue logic for icount	2010-07-24 13:40:05 +02:00
exec.h	move cpu_pc_from_tb to target-*/exec.h	2010-07-03 09:48:12 +03:00
helper.c	target-mips: fix xtlb exception for loongson	2010-07-17 16:13:12 +02:00
helper.h	target-mips: microMIPS ASE support	2010-06-09 16:10:50 +02:00
machine.c	target-mips: rename CP0_LLAddr into lladdr	2009-11-22 14:12:13 +01:00
mips-defs.h	MIPS: Initial support of fulong mini pc (CPU definition)	2010-06-29 23:07:52 +02:00
op_helper.c	mips: Correct MIPS interrupt glue logic for icount	2010-07-24 13:40:05 +02:00
translate.c	target-mips: add loongson 2E & 2F integer instructions	2010-07-11 10:24:31 +02:00
translate_init.c	MIPS: Initial support of fulong mini pc (CPU definition)	2010-06-29 23:07:52 +02:00