Mingwang Li 03fd0c5fe9 hw/riscv: virt: Use machine->ram as the system memory ... If default main_mem is used to be registered as the system memory, other memory cannot be initialized. Therefore, the system memory should be initialized to the machine->ram, which consists of the default main_mem and other possible memory required by applications, such as shared hugepage memory in DPDK. Also, the mc->defaul_ram_id should be set to the default main_mem, such as "riscv_virt_board.ram" for the virt machine. Signed-off-by: Mingwang Li <limingwang@huawei.com> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211016030908.40480-1-limingwang@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-22 07:47:51 +10:00
..
Kconfig	hw/intc: Rename sifive_clint sources to riscv_aclint sources	2021-09-21 07:56:49 +10:00
boot.c	hw/riscv/boot: Check the error of fdt_pack()	2021-07-15 09:35:46 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/riscv: opentitan: Correct the USB Dev address	2021-09-21 12:10:47 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: shakti_c: Mark as not user creatable	2021-10-07 08:41:33 +10:00
sifive_e.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
sifive_u.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
spike.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
virt.c	hw/riscv: virt: Use machine->ram as the system memory	2021-10-22 07:47:51 +10:00