mirror of https://github.com/xemu-project/xemu.git
2efff1c0dd
Currently the default PCI host bridge for the 'pseries' machine type is constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in guest memory space. This means that if > 1TiB of guest RAM is specified, the RAM will collide with the PCI IO windows, causing serious problems. Problems won't be obvious until guest RAM goes a bit beyond 1TiB, because there's a little unused space at the bottom of the area reserved for PCI, but essentially this means that > 1TiB of RAM has never worked with the pseries machine type. This patch fixes this by altering the placement of PHBs on large-RAM VMs. Instead of always placing the first PHB at 1TiB, it is placed at the next 1 TiB boundary after the maximum RAM address. Technically, this changes behaviour in a migration-breaking way for existing machines with > 1TiB maximum memory, but since having > 1 TiB memory was broken anyway, this seems like a reasonable trade-off. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> |
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| .. | ||
| Makefile.objs | ||
| e500-ccsr.h | ||
| e500.c | ||
| e500.h | ||
| e500plat.c | ||
| fdt.c | ||
| mac.h | ||
| mac_newworld.c | ||
| mac_oldworld.c | ||
| mpc8544_guts.c | ||
| mpc8544ds.c | ||
| ppc.c | ||
| ppc4xx_devs.c | ||
| ppc4xx_pci.c | ||
| ppc405.h | ||
| ppc405_boards.c | ||
| ppc405_uc.c | ||
| ppc440_bamboo.c | ||
| ppc_booke.c | ||
| ppce500_spin.c | ||
| prep.c | ||
| spapr.c | ||
| spapr_cpu_core.c | ||
| spapr_drc.c | ||
| spapr_events.c | ||
| spapr_hcall.c | ||
| spapr_iommu.c | ||
| spapr_pci.c | ||
| spapr_pci_vfio.c | ||
| spapr_rng.c | ||
| spapr_rtas.c | ||
| spapr_rtas_ddw.c | ||
| spapr_rtc.c | ||
| spapr_vio.c | ||
| trace-events | ||
| virtex_ml507.c | ||