Matheus Ferst 2c9f795841 target/ppc: Implement Vector Insert from VSR using GPR index insns ... Implements the following PowerISA v3.1 instructions: vinsbvlx: Vector Insert Byte from VSR using GPR-specified Left-Index vinshvlx: Vector Insert Halfword from VSR using GPR-specified Left-Index vinswvlx: Vector Insert Word from VSR using GPR-specified Left-Index vinsbvrx: Vector Insert Byte from VSR using GPR-specified Right-Index vinshvrx: Vector Insert Halfword from VSR using GPR-specified Right-Index vinswvrx: Vector Insert Word from VSR using GPR-specified Right-Index Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-8-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2021-11-09 10:32:52 +11:00
..
dfp-impl.c.inc	target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree	2021-11-09 10:32:52 +11:00
fixedpoint-impl.c.inc	target/ppc: Implement vclzdm/vctzdm instructions	2021-11-09 10:32:52 +11:00
fp-impl.c.inc	target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions	2021-11-09 10:32:51 +11:00
fp-ops.c.inc	target/ppc: Move load and store floating point instructions to decodetree	2021-11-09 10:32:51 +11:00
spe-impl.c.inc	ppc patch queue 2020-08-18	2020-08-24 09:35:21 +01:00
spe-ops.c.inc	meson: rename included C source files to .c.inc	2020-08-21 06:18:30 -04:00
vmx-impl.c.inc	target/ppc: Implement Vector Insert from VSR using GPR index insns	2021-11-09 10:32:52 +11:00
vmx-ops.c.inc	ppc patch queue 2020-08-18	2020-08-24 09:35:21 +01:00
vsx-impl.c.inc	target/ppc: Fix load endianness for lxvwsx/lxvdsx	2021-05-19 10:44:04 +10:00
vsx-ops.c.inc	ppc/translate: Implement lxvwsx opcode	2020-11-24 11:34:18 +11:00