mirror of https://github.com/xemu-project/xemu.git
24c3caff99
The POWER8 LPC ISA device irqs all get combined and reported to the line connected the PSI LPCHC irq. POWER9 changed this so only internal LPC host controller irqs use that line, and the device irqs get routed to 4 new lines connected to PSI SERIRQ0-3. POWER9 also introduced a new feature that automatically clears the irq status in the LPC host controller when EOI'ed, so software does not have to. The powernv OPAL (skiboot) firmware managed to work because the LPCHC irq handler scanned all LPC irqs and handled those including clearing status even on POWER9 systems. So LPC irqs worked despite OPAL thinking it was running in POWER9 mode. After this change, UART interrupts show up on serirq1 which is where OPAL routes them to: cat /proc/interrupts ... 20: 0 XIVE-IRQ 1048563 Level opal-psi#0:lpchc ... 25: 34 XIVE-IRQ 1048568 Level opal-psi#0:lpc_serirq_mux1 Whereas they previously turn up on lpchc. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> |
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| authz | ||
| block | ||
| chardev | ||
| crypto | ||
| disas | ||
| exec | ||
| fpu | ||
| gdbstub | ||
| hw | ||
| io | ||
| libdecnumber | ||
| migration | ||
| monitor | ||
| net | ||
| qapi | ||
| qemu | ||
| qom | ||
| scsi | ||
| semihosting | ||
| standard-headers | ||
| sysemu | ||
| tcg | ||
| ui | ||
| user | ||
| elf.h | ||
| glib-compat.h | ||
| qemu-io.h | ||
| qemu-main.h | ||