mirror of https://github.com/xemu-project/xemu.git
532 lines
16 KiB
C
532 lines
16 KiB
C
/*
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* x86 exception helpers - sysemu code
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "tcg/helper-tcg.h"
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typedef struct TranslateParams {
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target_ulong addr;
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target_ulong cr3;
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int pg_mode;
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int mmu_idx;
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MMUAccessType access_type;
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bool use_stage2;
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} TranslateParams;
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typedef struct TranslateResult {
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hwaddr paddr;
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int prot;
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int page_size;
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} TranslateResult;
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typedef enum TranslateFaultStage2 {
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S2_NONE,
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S2_GPA,
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S2_GPT,
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} TranslateFaultStage2;
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typedef struct TranslateFault {
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int exception_index;
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int error_code;
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target_ulong cr2;
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TranslateFaultStage2 stage2;
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} TranslateFault;
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#define PTE_HPHYS(ADDR) \
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do { \
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if (in->use_stage2) { \
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nested_in.addr = (ADDR); \
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if (!mmu_translate(env, &nested_in, out, err)) { \
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err->stage2 = S2_GPT; \
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return false; \
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} \
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(ADDR) = out->paddr; \
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} \
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} while (0)
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static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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TranslateResult *out, TranslateFault *err)
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{
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TranslateParams nested_in = {
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/* Use store for page table entries, to allow A/D flag updates. */
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.access_type = MMU_DATA_STORE,
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.cr3 = env->nested_cr3,
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.pg_mode = env->nested_pg_mode,
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.mmu_idx = MMU_USER_IDX,
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.use_stage2 = false,
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};
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CPUState *cs = env_cpu(env);
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X86CPU *cpu = env_archcpu(env);
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const int32_t a20_mask = x86_get_a20_mask(env);
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const target_ulong addr = in->addr;
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const int pg_mode = in->pg_mode;
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const bool is_user = (in->mmu_idx == MMU_USER_IDX);
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const MMUAccessType access_type = in->access_type;
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uint64_t ptep, pte;
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hwaddr pte_addr;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint32_t pkr;
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int page_size;
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if (!(pg_mode & PG_MODE_NXE)) {
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rsvd_mask |= PG_NX_MASK;
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}
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if (pg_mode & PG_MODE_PAE) {
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#ifdef TARGET_X86_64
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if (pg_mode & PG_MODE_LMA) {
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if (pg_mode & PG_MODE_LA57) {
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/*
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* Page table level 5
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*/
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pte_addr = ((in->cr3 & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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ptep = pte ^ PG_NX_MASK;
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} else {
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pte = in->cr3;
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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/*
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* Page table level 4
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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ptep &= pte ^ PG_NX_MASK;
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/*
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* Page table level 3
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 30) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pte ^ PG_NX_MASK;
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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if (pte & PG_PSE_MASK) {
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/* 1 GB page */
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page_size = 1024 * 1024 * 1024;
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goto do_check_protect;
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}
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} else
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#endif
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{
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/*
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* Page table level 3
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*/
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pte_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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rsvd_mask |= PG_HI_USER_MASK;
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if (pte & (rsvd_mask | PG_NX_MASK)) {
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goto do_fault_rsvd;
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}
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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/*
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* Page table level 2
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 21) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pte ^ PG_NX_MASK;
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if (pte & PG_PSE_MASK) {
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/* 2 MB page */
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page_size = 2048 * 1024;
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goto do_check_protect;
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}
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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/*
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* Page table level 1
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 12) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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/* combine pde and pte nx, user and rw protections */
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ptep &= pte ^ PG_NX_MASK;
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page_size = 4096;
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} else {
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/*
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* Page table level 2
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*/
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pte_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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ptep = pte | PG_NX_MASK;
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/* if PSE bit is set, then we use a 4MB page */
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if ((pte & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) {
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page_size = 4096 * 1024;
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/*
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* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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* Leave bits 20-13 in place for setting accessed/dirty bits below.
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*/
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pte = (uint32_t)pte | ((pte & 0x1fe000LL) << (32 - 13));
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rsvd_mask = 0x200000;
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goto do_check_protect_pse36;
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}
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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/*
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* Page table level 1
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*/
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pte_addr = ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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/* combine pde and pte user and rw protections */
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ptep &= pte | PG_NX_MASK;
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page_size = 4096;
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rsvd_mask = 0;
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}
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do_check_protect:
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rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
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do_check_protect_pse36:
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep ^= PG_NX_MASK;
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/* can the page can be put in the TLB? prot will tell us */
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if (is_user && !(ptep & PG_USER_MASK)) {
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goto do_fault_protect;
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}
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int prot = 0;
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if (in->mmu_idx != MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) {
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prot |= PAGE_READ;
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if ((ptep & PG_RW_MASK) || !(is_user || (pg_mode & PG_MODE_WP))) {
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prot |= PAGE_WRITE;
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}
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}
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if (!(ptep & PG_NX_MASK) &&
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(is_user ||
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!((pg_mode & PG_MODE_SMEP) && (ptep & PG_USER_MASK)))) {
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prot |= PAGE_EXEC;
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}
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if (ptep & PG_USER_MASK) {
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pkr = pg_mode & PG_MODE_PKE ? env->pkru : 0;
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} else {
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pkr = pg_mode & PG_MODE_PKS ? env->pkrs : 0;
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}
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if (pkr) {
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uint32_t pk = (pte & PG_PKRU_MASK) >> PG_PKRU_BIT;
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uint32_t pkr_ad = (pkr >> pk * 2) & 1;
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uint32_t pkr_wd = (pkr >> pk * 2) & 2;
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uint32_t pkr_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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if (pkr_ad) {
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pkr_prot &= ~(PAGE_READ | PAGE_WRITE);
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} else if (pkr_wd && (is_user || (pg_mode & PG_MODE_WP))) {
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pkr_prot &= ~PAGE_WRITE;
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}
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if ((pkr_prot & (1 << access_type)) == 0) {
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goto do_fault_pk_protect;
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}
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prot &= pkr_prot;
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}
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if ((prot & (1 << access_type)) == 0) {
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goto do_fault_protect;
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}
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/* yes, it can! */
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{
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uint32_t set = PG_ACCESSED_MASK;
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if (access_type == MMU_DATA_STORE) {
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set |= PG_DIRTY_MASK;
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}
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if (set & ~pte) {
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pte |= set;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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}
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if (!(pte & PG_DIRTY_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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assert(access_type != MMU_DATA_STORE);
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prot &= ~PAGE_WRITE;
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}
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/* align to page_size */
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out->paddr = (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1))
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| (addr & (page_size - 1));
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if (in->use_stage2) {
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nested_in.addr = out->paddr;
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nested_in.access_type = access_type;
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if (!mmu_translate(env, &nested_in, out, err)) {
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err->stage2 = S2_GPA;
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return false;
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}
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/* Merge stage1 & stage2 protection bits. */
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prot &= out->prot;
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/* Re-verify resulting protection. */
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if ((prot & (1 << access_type)) == 0) {
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goto do_fault_protect;
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}
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}
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out->prot = prot;
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out->page_size = page_size;
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return true;
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int error_code;
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do_fault_rsvd:
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error_code = PG_ERROR_RSVD_MASK;
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goto do_fault_cont;
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do_fault_protect:
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error_code = PG_ERROR_P_MASK;
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goto do_fault_cont;
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do_fault_pk_protect:
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assert(access_type != MMU_INST_FETCH);
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error_code = PG_ERROR_PK_MASK | PG_ERROR_P_MASK;
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goto do_fault_cont;
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do_fault:
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error_code = 0;
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do_fault_cont:
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if (is_user) {
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error_code |= PG_ERROR_U_MASK;
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}
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switch (access_type) {
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case MMU_DATA_LOAD:
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break;
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case MMU_DATA_STORE:
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error_code |= PG_ERROR_W_MASK;
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break;
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case MMU_INST_FETCH:
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if (pg_mode & (PG_MODE_NXE | PG_MODE_SMEP)) {
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error_code |= PG_ERROR_I_D_MASK;
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}
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break;
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}
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err->exception_index = EXCP0E_PAGE;
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err->error_code = error_code;
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err->cr2 = addr;
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err->stage2 = S2_NONE;
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return false;
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}
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static G_NORETURN void raise_stage2(CPUX86State *env, TranslateFault *err,
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uintptr_t retaddr)
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{
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uint64_t exit_info_1 = err->error_code;
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switch (err->stage2) {
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case S2_GPT:
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exit_info_1 |= SVM_NPTEXIT_GPT;
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break;
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case S2_GPA:
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exit_info_1 |= SVM_NPTEXIT_GPA;
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break;
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default:
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g_assert_not_reached();
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}
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x86_stq_phys(env_cpu(env),
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env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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err->cr2);
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, retaddr);
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}
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static bool get_physical_address(CPUX86State *env, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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TranslateResult *out, TranslateFault *err)
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{
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TranslateParams in;
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bool use_stage2 = env->hflags2 & HF2_NPT_MASK;
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in.addr = addr;
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in.access_type = access_type;
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switch (mmu_idx) {
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case MMU_PHYS_IDX:
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break;
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case MMU_NESTED_IDX:
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if (likely(use_stage2)) {
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in.cr3 = env->nested_cr3;
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in.pg_mode = env->nested_pg_mode;
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in.mmu_idx = MMU_USER_IDX;
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in.use_stage2 = false;
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if (!mmu_translate(env, &in, out, err)) {
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err->stage2 = S2_GPA;
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return false;
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}
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return true;
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}
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break;
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default:
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in.cr3 = env->cr[3];
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in.mmu_idx = mmu_idx;
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in.use_stage2 = use_stage2;
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in.pg_mode = get_pg_mode(env);
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if (likely(in.pg_mode)) {
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if (in.pg_mode & PG_MODE_LMA) {
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/* test virtual address sign extension */
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int shift = in.pg_mode & PG_MODE_LA57 ? 56 : 47;
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int64_t sext = (int64_t)addr >> shift;
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if (sext != 0 && sext != -1) {
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err->exception_index = EXCP0D_GPF;
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err->error_code = 0;
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err->cr2 = addr;
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return false;
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}
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}
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return mmu_translate(env, &in, out, err);
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}
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break;
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}
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/* Translation disabled. */
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out->paddr = addr & x86_get_a20_mask(env);
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#ifdef TARGET_X86_64
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if (!(env->hflags & HF_LMA_MASK)) {
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/* Without long mode we can only address 32bits in real mode */
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out->paddr = (uint32_t)out->paddr;
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}
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#endif
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out->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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out->page_size = TARGET_PAGE_SIZE;
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return true;
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}
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bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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CPUX86State *env = cs->env_ptr;
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TranslateResult out;
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TranslateFault err;
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if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err)) {
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/*
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* Even if 4MB pages, we map only one 4KB page in the cache to
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* avoid filling it too fast.
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*/
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assert(out.prot & (1 << access_type));
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tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK,
|
|
out.paddr & TARGET_PAGE_MASK,
|
|
cpu_get_mem_attrs(env),
|
|
out.prot, mmu_idx, out.page_size);
|
|
return true;
|
|
}
|
|
|
|
if (probe) {
|
|
return false;
|
|
}
|
|
|
|
if (err.stage2 != S2_NONE) {
|
|
raise_stage2(env, &err, retaddr);
|
|
}
|
|
|
|
if (env->intercept_exceptions & (1 << err.exception_index)) {
|
|
/* cr2 is not modified in case of exceptions */
|
|
x86_stq_phys(cs, env->vm_vmcb +
|
|
offsetof(struct vmcb, control.exit_info_2),
|
|
err.cr2);
|
|
} else {
|
|
env->cr[2] = err.cr2;
|
|
}
|
|
raise_exception_err_ra(env, err.exception_index, err.error_code, retaddr);
|
|
}
|
|
|
|
G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
|
|
MMUAccessType access_type,
|
|
int mmu_idx, uintptr_t retaddr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
handle_unaligned_access(&cpu->env, vaddr, access_type, retaddr);
|
|
}
|