Tomasz Jeznach 0c54acb824 hw/riscv: add RISC-V IOMMU base emulation ... The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add the foundation of the device emulation for RISC-V IOMMU. It includes support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage (sv32x4, sv39x4, sv48x4, sv57x4 caps). Other capabilities like ATS and DBG support will be added incrementally in the next patches. Co-developed-by: Sebastien Boeuf <seb@rivosinc.com> Signed-off-by: Sebastien Boeuf <seb@rivosinc.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jason Chien <jason.chien@sifive.com> Message-ID: <20241016204038.649340-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-10-31 13:51:24 +10:00
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Kconfig	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
boot.c	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	2024-10-30 11:22:07 +10:00
meson.build	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
microchip_pfsoc.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
numa.c	hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()	2024-02-09 20:43:14 +10:00
opentitan.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
riscv-iommu-bits.h	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
riscv-iommu.c	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
riscv-iommu.h	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
sifive_e.c	hw: Remove unused inclusion of hw/char/serial.h	2024-10-03 19:33:23 +02:00
sifive_u.c	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	2024-10-30 11:22:07 +10:00
spike.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
trace-events	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
trace.h	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
virt-acpi-build.c	hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART	2024-07-22 20:15:42 -04:00
virt.c	* pc: Add a description for the i8042 property	2024-10-04 19:28:37 +01:00