mirror of https://github.com/xemu-project/xemu.git
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/*
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* STM32 RCC (only reset and enable registers are implemented)
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*
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* Copyright (c) 2024 Román Cárdenas <rcardenas.rod@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_STM32_RCC_H
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#define HW_STM32_RCC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define STM32_RCC_CR 0x00
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#define STM32_RCC_PLL_CFGR 0x04
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#define STM32_RCC_CFGR 0x08
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#define STM32_RCC_CIR 0x0C
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#define STM32_RCC_AHB1_RSTR 0x10
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#define STM32_RCC_AHB2_RSTR 0x14
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#define STM32_RCC_AHB3_RSTR 0x18
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#define STM32_RCC_APB1_RSTR 0x20
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#define STM32_RCC_APB2_RSTR 0x24
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#define STM32_RCC_AHB1_ENR 0x30
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#define STM32_RCC_AHB2_ENR 0x34
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#define STM32_RCC_AHB3_ENR 0x38
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#define STM32_RCC_APB1_ENR 0x40
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#define STM32_RCC_APB2_ENR 0x44
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#define STM32_RCC_AHB1_LPENR 0x50
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#define STM32_RCC_AHB2_LPENR 0x54
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#define STM32_RCC_AHB3_LPENR 0x58
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#define STM32_RCC_APB1_LPENR 0x60
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#define STM32_RCC_APB2_LPENR 0x64
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#define STM32_RCC_BDCR 0x70
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#define STM32_RCC_CSR 0x74
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#define STM32_RCC_SSCGR 0x80
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#define STM32_RCC_PLLI2SCFGR 0x84
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#define STM32_RCC_PLLSAI_CFGR 0x88
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#define STM32_RCC_DCKCFGR 0x8C
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#define STM32_RCC_CKGATENR 0x90
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#define STM32_RCC_DCKCFGR2 0x94
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#define STM32_RCC_NREGS ((STM32_RCC_DCKCFGR2 >> 2) + 1)
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#define STM32_RCC_PERIPHERAL_SIZE 0x400
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#define STM32_RCC_NIRQS (32 * 5) /* 32 bits per reg, 5 en/rst regs */
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#define STM32_RCC_GPIO_IRQ_OFFSET 0
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#define TYPE_STM32_RCC "stm32.rcc"
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typedef struct STM32RccState STM32RccState;
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DECLARE_INSTANCE_CHECKER(STM32RccState, STM32_RCC, TYPE_STM32_RCC)
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#define NUM_GPIO_EVENT_IN_LINES 16
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struct STM32RccState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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uint32_t regs[STM32_RCC_NREGS];
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qemu_irq enable_irq[STM32_RCC_NIRQS];
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qemu_irq reset_irq[STM32_RCC_NIRQS];
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};
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#endif /* HW_STM32_RCC_H */
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