mirror of https://github.com/xemu-project/xemu.git
121 lines
3.4 KiB
C
121 lines
3.4 KiB
C
/*
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* QEMU Geforce NV2A implementation
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*
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* Copyright (c) 2012 espes
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* Copyright (c) 2015 Jannik Vogel
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* Copyright (c) 2018-2021 Matt Borgerson
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "nv2a_int.h"
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/* USER - PFIFO MMIO and DMA submission area */
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uint64_t user_read(void *opaque, hwaddr addr, unsigned int size)
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{
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NV2AState *d = (NV2AState *)opaque;
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unsigned int channel_id = addr >> 16;
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assert(channel_id < NV2A_NUM_CHANNELS);
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qemu_mutex_lock(&d->pfifo.lock);
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uint32_t channel_modes = d->pfifo.regs[NV_PFIFO_MODE];
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uint64_t r = 0;
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if (channel_modes & (1 << channel_id)) {
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/* DMA Mode */
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unsigned int cur_channel_id =
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GET_MASK(d->pfifo.regs[NV_PFIFO_CACHE1_PUSH1],
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NV_PFIFO_CACHE1_PUSH1_CHID);
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if (channel_id == cur_channel_id) {
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switch (addr & 0xFFFF) {
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case NV_USER_DMA_PUT:
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r = d->pfifo.regs[NV_PFIFO_CACHE1_DMA_PUT];
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break;
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case NV_USER_DMA_GET:
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r = d->pfifo.regs[NV_PFIFO_CACHE1_DMA_GET];
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break;
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case NV_USER_REF:
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r = d->pfifo.regs[NV_PFIFO_CACHE1_REF];
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break;
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default:
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break;
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}
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} else {
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/* ramfc */
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assert(false);
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}
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} else {
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/* PIO Mode */
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assert(false);
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}
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qemu_mutex_unlock(&d->pfifo.lock);
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nv2a_reg_log_read(NV_USER, addr, size, r);
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return r;
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}
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void user_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
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{
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NV2AState *d = (NV2AState *)opaque;
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nv2a_reg_log_write(NV_USER, addr, size, val);
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unsigned int channel_id = addr >> 16;
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assert(channel_id < NV2A_NUM_CHANNELS);
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qemu_mutex_lock(&d->pfifo.lock);
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uint32_t channel_modes = d->pfifo.regs[NV_PFIFO_MODE];
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if (channel_modes & (1 << channel_id)) {
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/* DMA Mode */
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unsigned int cur_channel_id =
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GET_MASK(d->pfifo.regs[NV_PFIFO_CACHE1_PUSH1],
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NV_PFIFO_CACHE1_PUSH1_CHID);
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if (channel_id == cur_channel_id) {
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switch (addr & 0xFFFF) {
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case NV_USER_DMA_PUT:
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d->pfifo.regs[NV_PFIFO_CACHE1_DMA_PUT] = val;
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break;
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case NV_USER_DMA_GET:
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d->pfifo.regs[NV_PFIFO_CACHE1_DMA_GET] = val;
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break;
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case NV_USER_REF:
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d->pfifo.regs[NV_PFIFO_CACHE1_REF] = val;
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break;
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default:
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assert(false);
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break;
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}
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pfifo_kick(d);
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} else {
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/* ramfc */
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assert(false);
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}
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} else {
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/* PIO Mode */
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assert(false);
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}
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qemu_mutex_unlock(&d->pfifo.lock);
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}
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