mirror of https://github.com/xemu-project/xemu.git
74 lines
2.0 KiB
C
74 lines
2.0 KiB
C
/*
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* QEMU Geforce NV2A implementation
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*
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* Copyright (c) 2012 espes
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* Copyright (c) 2015 Jannik Vogel
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* Copyright (c) 2018-2021 Matt Borgerson
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "nv2a_int.h"
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/* PMC - card master control */
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uint64_t pmc_read(void *opaque, hwaddr addr, unsigned int size)
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{
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NV2AState *d = (NV2AState *)opaque;
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uint64_t r = 0;
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switch (addr) {
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case NV_PMC_BOOT_0:
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/* chipset and stepping:
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* NV2A, A03, Rev 0 */
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r = 0x02A000A3;
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break;
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case NV_PMC_INTR_0:
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/* Shows which functional units have pending IRQ */
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r = d->pmc.pending_interrupts;
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break;
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case NV_PMC_INTR_EN_0:
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/* Selects which functional units can cause IRQs */
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r = d->pmc.enabled_interrupts;
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break;
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default:
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break;
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}
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nv2a_reg_log_read(NV_PMC, addr, size, r);
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return r;
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}
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void pmc_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
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{
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NV2AState *d = (NV2AState *)opaque;
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nv2a_reg_log_write(NV_PMC, addr, size, val);
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switch (addr) {
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case NV_PMC_INTR_0:
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/* the bits of the interrupts to clear are wrtten */
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d->pmc.pending_interrupts &= ~val;
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nv2a_update_irq(d);
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break;
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case NV_PMC_INTR_EN_0:
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d->pmc.enabled_interrupts = val;
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nv2a_update_irq(d);
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break;
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default:
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break;
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}
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}
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