mirror of https://github.com/xemu-project/xemu.git
268 lines
12 KiB
C
268 lines
12 KiB
C
/*
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* QEMU nForce Ethernet Controller register definitions
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*
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* Copyright (c) 2013 espes
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* Copyright (c) 2015-2025 Matt Borgerson
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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* --
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*
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* Most definitions are based on forcedeth.c, taken from cromwell project.
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* Original forcedeth.c license follows:
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*
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* --
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* forcedeth.c -- Etherboot device driver for the NVIDIA nForce
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* media access controllers.
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*
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* Note: This driver is based on the Linux driver that was based on
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* a cleanroom reimplementation which was based on reverse
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* engineered documentation written by Carl-Daniel Hailfinger
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* and Andrew de Quincey. It's neither supported nor endorsed
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* by NVIDIA Corp. Use at your own risk.
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*
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* Written 2004 by Timothy Legge <tlegge@rogers.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Portions of this code based on:
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* forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
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*
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* (C) 2003 Manfred Spraul
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* See Linux Driver for full information
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*
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* Linux Driver Version 0.22, 19 Jan 2004
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*
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*
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* REVISION HISTORY:
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* ================
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* v1.0 01-31-2004 timlegge Initial port of Linux driver
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* v1.1 02-03-2004 timlegge Large Clean up, first release
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*
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* Indent Options: indent -kr -i8
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***************************************************************************/
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#ifndef HW_NVNET_REGS_H
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#define HW_NVNET_REGS_H
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// clang-format off
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#define NVNET_IRQ_STATUS 0x000
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# define NVNET_IRQ_STATUS_RX 0x00000002
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# define NVNET_IRQ_STATUS_RX_NOBUF 0x00000004
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# define NVNET_IRQ_STATUS_TX_ERR 0x00000008
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# define NVNET_IRQ_STATUS_TX 0x00000010
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# define NVNET_IRQ_STATUS_TIMER 0x00000020
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# define NVNET_IRQ_STATUS_MIIEVENT 0x00000040
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#define NVNET_IRQ_MASK 0x004
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#define NVNET_UNKNOWN_SETUP_REG6 0x008
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# define NVNET_UNKNOWN_SETUP_REG6_VAL 3
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/*
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* NVNET_POLLING_INTERVAL_DEFAULT is the interval length of the timer source on the nic
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* NVNET_POLLING_INTERVAL_DEFAULT=97 would result in an interval length of 1 ms
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*/
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#define NVNET_POLLING_INTERVAL 0x00C
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# define NVNET_POLLING_INTERVAL_DEFAULT 970
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#define NVNET_MISC1 0x080
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# define NVNET_MISC1_HD 0x00000002
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# define NVNET_MISC1_FORCE 0x003B0F3C
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#define NVNET_TRANSMITTER_CONTROL 0x084
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# define NVNET_TRANSMITTER_CONTROL_START 0x00000001
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#define NVNET_TRANSMITTER_STATUS 0x088
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# define NVNET_TRANSMITTER_STATUS_BUSY 0x00000001
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#define NVNET_PACKET_FILTER 0x08C
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# define NVNET_PACKET_FILTER_ALWAYS 0x007F0008
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# define NVNET_PACKET_FILTER_PROMISC 0x00000080
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# define NVNET_PACKET_FILTER_MYADDR 0x00000020
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#define NVNET_OFFLOAD 0x090
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# define NVNET_OFFLOAD_HOMEPHY 0x00000601
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# define NVNET_OFFLOAD_NORMAL 0x000005EE
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#define NVNET_RECEIVER_CONTROL 0x094
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# define NVNET_RECEIVER_CONTROL_START 0x00000001
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#define NVNET_RECEIVER_STATUS 0x098
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# define NVNET_RECEIVER_STATUS_BUSY 0x00000001
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#define NVNET_RANDOM_SEED 0x09C
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# define NVNET_RANDOM_SEED_MASK 0x000000FF
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# define NVNET_RANDOM_SEED_FORCE 0x00007F00
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#define NVNET_UNKNOWN_SETUP_REG1 0x0A0
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# define NVNET_UNKNOWN_SETUP_REG1_VAL 0x0016070F
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#define NVNET_UNKNOWN_SETUP_REG2 0x0A4
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# define NVNET_UNKNOWN_SETUP_REG2_VAL 0x00000016
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#define NVNET_MAC_ADDR_A 0x0A8
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#define NVNET_MAC_ADDR_B 0x0AC
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#define NVNET_MULTICAST_ADDR_A 0x0B0
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# define NVNET_MULTICAST_ADDR_A_FORCE 0x00000001
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#define NVNET_MULTICAST_ADDR_B 0x0B4
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#define NVNET_MULTICAST_MASK_A 0x0B8
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#define NVNET_MULTICAST_MASK_B 0x0BC
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#define NVNET_TX_RING_PHYS_ADDR 0x100
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#define NVNET_RX_RING_PHYS_ADDR 0x104
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#define NVNET_RING_SIZE 0x108
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# define NVNET_RING_SIZE_TX 0x0000FFFF
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# define NVNET_RING_SIZE_RX 0xFFFF0000
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#define NVNET_UNKNOWN_TRANSMITTER_REG 0x10C
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#define NVNET_LINKSPEED 0x110
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# define NVNET_LINKSPEED_FORCE 0x00010000
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# define NVNET_LINKSPEED_10 10
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# define NVNET_LINKSPEED_100 100
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# define NVNET_LINKSPEED_1000 1000
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#define NVNET_TX_RING_CURRENT_DESC_PHYS_ADDR 0x11C
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#define NVNET_RX_RING_CURRENT_DESC_PHYS_ADDR 0x120
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#define NVNET_TX_CURRENT_BUFFER_PHYS_ADDR 0x124
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#define NVNET_RX_CURRENT_BUFFER_PHYS_ADDR 0x12C
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#define NVNET_UNKNOWN_SETUP_REG5 0x130
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# define NVNET_UNKNOWN_SETUP_REG5_BIT31 (1 << 31)
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#define NVNET_TX_RING_NEXT_DESC_PHYS_ADDR 0x134
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#define NVNET_RX_RING_NEXT_DESC_PHYS_ADDR 0x138
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#define NVNET_UNKNOWN_SETUP_REG8 0x13C
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# define NVNET_UNKNOWN_SETUP_REG8_VAL1 0x00300010
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#define NVNET_UNKNOWN_SETUP_REG7 0x140
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# define NVNET_UNKNOWN_SETUP_REG7_VAL 0x00300010
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#define NVNET_TX_RX_CONTROL 0x144
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# define NVNET_TX_RX_CONTROL_KICK 0x00000001
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# define NVNET_TX_RX_CONTROL_BIT1 0x00000002
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# define NVNET_TX_RX_CONTROL_BIT2 0x00000004
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# define NVNET_TX_RX_CONTROL_IDLE 0x00000008
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# define NVNET_TX_RX_CONTROL_RESET 0x00000010
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#define NVNET_MII_STATUS 0x180
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# define NVNET_MII_STATUS_ERROR 0x00000001
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# define NVNET_MII_STATUS_LINKCHANGE 0x00000008
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#define NVNET_UNKNOWN_SETUP_REG4 0x184
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# define NVNET_UNKNOWN_SETUP_REG4_VAL 8
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#define NVNET_ADAPTER_CONTROL 0x188
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# define NVNET_ADAPTER_CONTROL_START 0x00000002
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# define NVNET_ADAPTER_CONTROL_LINKUP 0x00000004
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# define NVNET_ADAPTER_CONTROL_PHYVALID 0x00004000
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# define NVNET_ADAPTER_CONTROL_RUNNING 0x00100000
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# define NVNET_ADAPTER_CONTROL_PHYSHIFT 24
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#define NVNET_MII_SPEED 0x18C
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# define NVNET_MII_SPEED_BIT8 (1 << 8)
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# define NVNET_MII_SPEED_DELAY 5
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#define NVNET_MDIO_ADDR 0x190
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# define NVNET_MDIO_ADDR_INUSE 0x00008000
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# define NVNET_MDIO_ADDR_WRITE 0x00000400
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# define NVNET_MDIO_ADDR_PHYADDR 0x000003E0
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# define NVNET_MDIO_ADDR_PHYREG 0x0000001F
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#define NVNET_MDIO_DATA 0x194
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#define NVNET_WAKEUPFLAGS 0x200
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# define NVNET_WAKEUPFLAGS_VAL 0x00007770
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# define NVNET_WAKEUPFLAGS_BUSYSHIFT 24
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# define NVNET_WAKEUPFLAGS_ENABLESHIFT 16
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# define NVNET_WAKEUPFLAGS_D3SHIFT 12
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# define NVNET_WAKEUPFLAGS_D2SHIFT 8
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# define NVNET_WAKEUPFLAGS_D1SHIFT 4
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# define NVNET_WAKEUPFLAGS_D0SHIFT 0
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# define NVNET_WAKEUPFLAGS_ACCEPT_MAGPAT 0x00000001
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# define NVNET_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x00000002
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# define NVNET_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x00000004
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#define NVNET_PATTERN_CRC 0x204
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#define NVNET_PATTERN_MASK 0x208
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#define NVNET_POWERCAP 0x268
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# define NVNET_POWERCAP_D3SUPP (1 << 30)
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# define NVNET_POWERCAP_D2SUPP (1 << 26)
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# define NVNET_POWERCAP_D1SUPP (1 << 25)
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#define NVNET_POWERSTATE 0x26C
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# define NVNET_POWERSTATE_POWEREDUP 0x00008000
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# define NVNET_POWERSTATE_VALID 0x00000100
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# define NVNET_POWERSTATE_MASK 0x00000003
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# define NVNET_POWERSTATE_D0 0x00000000
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# define NVNET_POWERSTATE_D1 0x00000001
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# define NVNET_POWERSTATE_D2 0x00000002
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# define NVNET_POWERSTATE_D3 0x00000003
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#define NV_TX_LASTPACKET (1 << 0)
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#define NV_TX_RETRYERROR (1 << 3)
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#define NV_TX_LASTPACKET1 (1 << 8)
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#define NV_TX_DEFERRED (1 << 10)
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#define NV_TX_CARRIERLOST (1 << 11)
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#define NV_TX_LATECOLLISION (1 << 12)
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#define NV_TX_UNDERFLOW (1 << 13)
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#define NV_TX_ERROR (1 << 14)
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#define NV_TX_VALID (1 << 15)
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#define NV_RX_DESCRIPTORVALID (1 << 0)
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#define NV_RX_MISSEDFRAME (1 << 1)
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#define NV_RX_SUBSTRACT1 (1 << 3)
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#define NV_RX_BIT4 (1 << 4)
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#define NV_RX_ERROR1 (1 << 7)
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#define NV_RX_ERROR2 (1 << 8)
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#define NV_RX_ERROR3 (1 << 9)
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#define NV_RX_ERROR4 (1 << 10)
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#define NV_RX_CRCERR (1 << 11)
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#define NV_RX_OVERFLOW (1 << 12)
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#define NV_RX_FRAMINGERR (1 << 13)
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#define NV_RX_ERROR (1 << 14)
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#define NV_RX_AVAIL (1 << 15)
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/* Miscelaneous hardware related defines: */
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#define NV_PCI_REGSZ 0x270
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/* various timeout delays: all in usec */
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#define NV_TXRX_RESET_DELAY 4
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#define NV_TXSTOP_DELAY1 10
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#define NV_TXSTOP_DELAY1MAX 500000
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#define NV_TXSTOP_DELAY2 100
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#define NV_RXSTOP_DELAY1 10
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#define NV_RXSTOP_DELAY1MAX 500000
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#define NV_RXSTOP_DELAY2 100
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#define NV_SETUP5_DELAY 5
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#define NV_SETUP5_DELAYMAX 50000
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#define NV_POWERUP_DELAY 5
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#define NV_POWERUP_DELAYMAX 5000
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#define NV_MIIBUSY_DELAY 50
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#define NV_MIIPHY_DELAY 10
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#define NV_MIIPHY_DELAYMAX 10000
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#define NV_WAKEUPPATTERNS 5
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#define NV_WAKEUPMASKENTRIES 4
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/* General driver defaults */
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#define NV_WATCHDOG_TIMEO (2 * HZ)
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#define DEFAULT_MTU 1500
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#define RX_RING 4
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#define TX_RING 2
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/* limited to 1 packet until we understand NV_TX_LASTPACKET */
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#define TX_LIMIT_STOP 10
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#define TX_LIMIT_START 5
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/* rx / tx mac addr + type + vlan + align + slack*/
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#define RX_NIC_BUFSIZE (DEFAULT_MTU + 64)
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/* even more slack */
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#define RX_ALLOC_BUFSIZE (DEFAULT_MTU + 128)
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#define TX_ALLOC_BUFSIZE (DEFAULT_MTU + 128)
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#define OOM_REFILL (1 + HZ / 20)
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#define POLL_WAIT (1 + HZ / 100)
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/* Link partner ability register. */
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#define LPA_SLCT 0x001F /* Same as advertise selector */
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#define LPA_RESV 0x1C00 /* Unused... */
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#define LPA_RFAULT 0x2000 /* Link partner faulted */
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#define LPA_NPAGE 0x8000 /* Next page bit */
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// clang-format on
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#endif /* HW_NVNET_REGS_H */
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