mirror of https://github.com/xemu-project/xemu.git
1362 Commits
| Author | SHA1 | Message | Date |
|---|---|---|---|
Peter Maydell
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c90cfb5294 |
Migartion pull request for 20240304
- Bryan's fix on multifd compression level API - Fabiano's mapped-ram series (base + multifd only) - Steve's amend on cpr document in qapi/ -----BEGIN PGP SIGNATURE----- iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZeUjKhIccGV0ZXJ4QHJl ZGhhdC5jb20ACgkQO1/MzfOr1wbv5QD/ZexBUsmZA5qyxgGvZ2yvlUBEGNOvtmKY kRdiYPU7khMA/0N43rn4LcqKCoq4+T+EAnYizGjIyhH/7BRUyn4DUxgO =AeEn -----END PGP SIGNATURE----- Merge tag 'migration-next-pull-request' of https://gitlab.com/peterx/qemu into staging Migartion pull request for 20240304 - Bryan's fix on multifd compression level API - Fabiano's mapped-ram series (base + multifd only) - Steve's amend on cpr document in qapi/ # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZeUjKhIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wbv5QD/ZexBUsmZA5qyxgGvZ2yvlUBEGNOvtmKY # kRdiYPU7khMA/0N43rn4LcqKCoq4+T+EAnYizGjIyhH/7BRUyn4DUxgO # =AeEn # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Mar 2024 01:26:02 GMT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [marginal] # gpg: aka "Peter Xu <peterx@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'migration-next-pull-request' of https://gitlab.com/peterx/qemu: (27 commits) migration/multifd: Document two places for mapped-ram tests/qtest/migration: Add a multifd + mapped-ram migration test migration/multifd: Add mapped-ram support to fd: URI migration/multifd: Support incoming mapped-ram stream format migration/multifd: Support outgoing mapped-ram stream format migration/multifd: Prepare multifd sync for mapped-ram migration migration/multifd: Add incoming QIOChannelFile support migration/multifd: Add outgoing QIOChannelFile support migration/multifd: Add a wrapper for channels_created migration/multifd: Allow receiving pages without packets migration/multifd: Allow multifd without packets migration/multifd: Decouple recv method from pages migration/multifd: Rename MultiFDSend|RecvParams::data to compress_data tests/qtest/migration: Add tests for mapped-ram file-based migration migration/ram: Add incoming 'mapped-ram' migration migration/ram: Add outgoing 'mapped-ram' migration migration: Add mapped-ram URI compatibility check migration/ram: Introduce 'mapped-ram' migration capability migration/qemu-file: add utility methods for working with seekable channels io: fsync before closing a file channel ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # migration/ram.c |
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Fabiano Rosas
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7a09f09283 |
tests/qtest/migration: Add a multifd + mapped-ram migration test
Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20240229153017.2221-24-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
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Fabiano Rosas
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c7076ec350 |
tests/qtest/migration: Add tests for mapped-ram file-based migration
Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20240229153017.2221-12-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
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Daniel Henrique Barboza
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3283843a8e |
libqos/virtio.c: fix 'avail_event' offset in qvring_init()
In qvring_init() we're writing vq->used->avail_event at "vq->used + 2 +
array_size". The struct pointed by vq->used is, from virtio_ring.h
Linux header):
* // A ring of used descriptor heads with free-running index.
* __virtio16 used_flags;
* __virtio16 used_idx;
* struct vring_used_elem used[num];
* __virtio16 avail_event_idx;
So 'flags' is the word right at vq->used. 'idx' is vq->used + 2. We need
to skip 'used_idx' by adding + 2 bytes, and then sum the vector size, to
reach avail_event_idx. An example on how to properly access this field
can be found in qvirtqueue_kick():
avail_event = qvirtio_readw(d, qts, vq->used + 4 +
sizeof(struct vring_used_elem) * vq->size);
This error was detected when enabling the RISC-V 'virt' libqos machine.
The 'idx' test from vhost-user-blk-test.c errors out with a timeout in
qvirtio_wait_used_elem(). The timeout happens because when processing
the first element, 'avail_event' is read in qvirtqueue_kick() as non-zero
because we didn't initialize it properly (and the memory at that point
happened to be non-zero). 'idx' is 0.
All of this makes this condition fail because "idx - avail_event" will
overflow and be non-zero:
/* < 1 because we add elements to avail queue one by one */
if ((flags & VRING_USED_F_NO_NOTIFY) == 0 &&
(!vq->event || (uint16_t)(idx-avail_event) < 1)) {
d->bus->virtqueue_kick(d, vq);
}
As a result the virtqueue is never kicked and we'll timeout waiting for it.
Fixes:
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Daniel Henrique Barboza
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2791490de1 |
libqos/virtio.c: init all elems in qvring_indirect_desc_setup()
The loop isn't setting the values for the last element. Every other
element is being initialized with addr = 0, flags = VRING_DESC_F_NEXT
and next = i + 1. The last elem is never touched.
This became a problem when enabling a RISC-V 'virt' libqos machine in
the 'indirect' test of virti-blk-test.c. The 'flags' for the last
element will end up being an odd number (since we didn't touch it).
Being an odd number it will be mistaken by VRING_DESC_F_NEXT, which
happens to be 1.
Deep into hw/virt/virtio.c, in virtqueue_split_pop(), into
virtqueue_split_read_next_desc(), a check for VRING_DESC_F_NEXT will be
made to see if we're supposed to chain. The code will keep up chaining
in the last element because the uninitialized value happens to be odd.
We'll error out right after that because desc->next (which is also
uninitialized) will be >= max. A VIRTQUEUE_READ_DESC_ERROR will be
returned, with an error message like this in the stderr:
qemu-system-riscv64: Desc next is 49391
Since we never returned, we'll end up timing out at qvirtio_wait_used_elem():
ERROR:../tests/qtest/libqos/virtio.c:236:qvirtio_wait_used_elem:
assertion failed: (g_get_monotonic_time() - start_time <= timeout_us)
The root cause is using uninitialized values from guest_alloc() in
qvring_indirect_desc_setup(). There's no guarantee that the memory pages
retrieved will be zeroed, so we can't make assumptions. In fact, commit
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Bryan Zhang
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2b57143231 |
tests/migration: Set compression level in migration tests
Adds calls to set compression level for `zstd` and `zlib` migration tests, just to make sure that the calls work. Signed-off-by: Bryan Zhang <bryan.zhang@bytedance.com> Link: https://lore.kernel.org/r/20240301035901.4006936-3-bryan.zhang@bytedance.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Fabiano Rosas
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6d79bd6818 |
tests/qtest/migration: Add a fd + file test
The fd URI supports an fd that is backed by a file. The code should select between QIOChannelFile and QIOChannelSocket, depending on the type of the fd. Add a test for that. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240220224138.24759-4-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
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Fabiano Rosas
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85cf9abd86 |
tests/qtest/migration: Rename fd_proto test
Next patch adds another fd test. Rename the existing one closer to what's used on other tests, with the 'precopy' prefix. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240220224138.24759-3-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
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Inès Varhol
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397424f87f |
tests/qtest: Check that EXTI fan-in irqs are correctly connected
This commit adds a QTest that verifies each input line of a specific EXTI OR gate can influence the output line. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240220184145.106107-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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dd88d696cc |
* m68k: Fix exception frame format for 68010
* Add cdrom test for LoongArch virt machine * Fix qtests when using --without-default-devices * Enable -Wvla * Windows 32-bit removal * Silence warnings in the test-x86-cpuid-compat qtest -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmXY7MMRHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbWkRg//TCprQ7Gesex/yvMFIZuZk+poEaibxGXU cWp6hneV8selTzBKzBC3VS1n31shd9astNRE95N2fSIfCV6R22y2tfZF2rSOoeog bvqX7KoaEnSsrDS054EGAnuvYQpOGLGth/3Mc9Z791r5I1tYZPJocVnAyi/OB+3q Gr5WzXj6Z/QD7c0f6vZ943wRBO/zc1729KikDUSyfS3Tua+15mAuUIUQdlLNNPct 6aT5e6c967mAYh93AUevd3hgVYXH2W4fH7s1q2pap2hMBw2a43XvlMKJ9CvXPFPg eU6knRPES16BSC2TTphNCBQi9n3rQdion01VsoQEetVBfFa4yA1Ys7ofF5vCa2l8 5EO5X3VQfZeq0ktmrLM7qAO0OMnolIqbeNS97ggOiyL0Q3YXim6cNWf8+OZbGoFR OK88ndmzEXrZq+5w4QBDGLHFU3u8ZeWAM6p7Ht/ZN89ndDYT5bGBwkjVRW5hVgck fmGhgutSqP2/DN5/4nMn8jtmGc65H/rBRilttW8W2JF72rQJYduDnx/A4KUatkHT tC58NwLarF3kF7cebhWvNQDD74ia/35n+fEAmtIHF42YHE6aifss91QrgT+qGG5+ GG12JIoFVDCgE1pkNU7GO53Uqo94Ej8TUOxwF9QfftxnqiktMG7Y/KQRcSA5VvHr laagGgDzHP0= =1hu9 -----END PGP SIGNATURE----- Merge tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu into staging * m68k: Fix exception frame format for 68010 * Add cdrom test for LoongArch virt machine * Fix qtests when using --without-default-devices * Enable -Wvla * Windows 32-bit removal * Silence warnings in the test-x86-cpuid-compat qtest # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmXY7MMRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWkRg//TCprQ7Gesex/yvMFIZuZk+poEaibxGXU # cWp6hneV8selTzBKzBC3VS1n31shd9astNRE95N2fSIfCV6R22y2tfZF2rSOoeog # bvqX7KoaEnSsrDS054EGAnuvYQpOGLGth/3Mc9Z791r5I1tYZPJocVnAyi/OB+3q # Gr5WzXj6Z/QD7c0f6vZ943wRBO/zc1729KikDUSyfS3Tua+15mAuUIUQdlLNNPct # 6aT5e6c967mAYh93AUevd3hgVYXH2W4fH7s1q2pap2hMBw2a43XvlMKJ9CvXPFPg # eU6knRPES16BSC2TTphNCBQi9n3rQdion01VsoQEetVBfFa4yA1Ys7ofF5vCa2l8 # 5EO5X3VQfZeq0ktmrLM7qAO0OMnolIqbeNS97ggOiyL0Q3YXim6cNWf8+OZbGoFR # OK88ndmzEXrZq+5w4QBDGLHFU3u8ZeWAM6p7Ht/ZN89ndDYT5bGBwkjVRW5hVgck # fmGhgutSqP2/DN5/4nMn8jtmGc65H/rBRilttW8W2JF72rQJYduDnx/A4KUatkHT # tC58NwLarF3kF7cebhWvNQDD74ia/35n+fEAmtIHF42YHE6aifss91QrgT+qGG5+ # GG12JIoFVDCgE1pkNU7GO53Uqo94Ej8TUOxwF9QfftxnqiktMG7Y/KQRcSA5VvHr # laagGgDzHP0= # =1hu9 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 23 Feb 2024 19:06:43 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu: target/i386: do not filter processor tracing features except on KVM .gitlab-ci.d/windows.yml: Remove shared-msys2 abstraction .gitlab-ci.d: Drop cross-win32-system job docs: Document that 32-bit Windows is unsupported meson: Enable -Wvla target/ppc/kvm: Replace variable length array in kvmppc_read_hptes() target/ppc/kvm: Replace variable length array in kvmppc_save_htab() tests: skip dbus-display tests that need a console tests/qtest: Fix boot-serial-test when using --without-default-devices tests/cdrom-test: Add cdrom test for LoongArch virt machine target/m68k: Fix exception frame format for 68010 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Glenn Miles
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4d2cd2d869 |
ppc/pnv: Test pnv i2c master and connected devices
Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset
Tests the following for powernv10-ranier only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Connected GPIO pin tests of P10 PCA9552 device. Tests
output of pins 0-4 affect input of pins 5-9 respectively.
- PCA9554 GPIO pins test. Tests input and ouput functionality.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Glenn Miles
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7b99fb30b3 |
misc/pca9552: Fix inverted input status
The pca9552 INPUT0 and INPUT1 registers are supposed to hold the logical values of the LED pins. A logical 0 should be seen in the INPUT0/1 registers for a pin when its corresponding LSn bits are set to 0, which is also the state needed for turning on an LED in a typical usage scenario. Existing code was doing the opposite and setting INPUT0/1 bit to a 1 when the LSn bit was set to 0, so this commit fixes that. Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> |
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Marc-André Lureau
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0e9a89193d |
tests: skip dbus-display tests that need a console
When compiling with "configure --without-default-devices", the dbus-display-test fails since it implicitly assumes that the machine comes with a default console. There doesn't seem to be an easy way to figure this during build time, so skip the tests requiring the Console interface at runtime. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20240221073759.171443-1-marcandre.lureau@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Thomas Huth
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1172428fb1 |
tests/qtest: Fix boot-serial-test when using --without-default-devices
If "configure" has been run with "--without-default-devices", there is no e1000 device in the binaries, so the boot-serial-test currently fails in that case since it tries to use the e1000 with the sam460ex machine. Since we're testing the serial output here, and not the NIC, let's simply switch to the "pci-bridge" device here instead, which should always be there for PCI-based machines like the sam460ex. Message-ID: <20240219111030.384158-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Bibo Mao
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0b76a1a959 |
tests/cdrom-test: Add cdrom test for LoongArch virt machine
The cdrom test skips to execute on LoongArch system with command "make check", this patch enables cdrom test for LoongArch virt machine platform. With this patch, cdrom test passes to run on LoongArch virt machine type. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20240217100230.134042-1-maobibo@loongson.cn> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Akihiko Odaki
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186acfbaf7 |
tests/qtest: Depend on dbus_display1_dep
It ensures dbus-display1.c will not be recompiled. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20240214-dbus-v7-3-7eff29f04c34@daynix.com> |
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Nabih Estefan
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bfe30b02e7 |
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead of 8xx. Also fix comments referencing this and values expecting 8xx. Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8 Signed-Off-By: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240208194759.2858582-2-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: commit message tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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bf25d7815b |
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
Currently QEMU will warn if there is a NIC on the board that is not connected to a backend. By default the '-nic user' will get used for all NICs, but if you manually connect a specific NIC to a specific backend, then the other NICs on the board have no backend and will be warned about: qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer qemu-system-arm: warning: nic npcm-gmac.0 has no peer qemu-system-arm: warning: nic npcm-gmac.1 has no peer So suppress those warnings by manually connecting every NIC on the board to some backend. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20240206171231.396392-3-peter.maydell@linaro.org |
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Peter Maydell
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ea2fde5bcc |
tests/qtest/bios-tables-tests: Update virt golden reference
Update the virt golden reference files to say that the FACP is ACPI
v6.3, and the GTDT table is a revision 3 table with space for the
virtual EL2 timer.
Diffs from iasl:
@@ -1,32 +1,32 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
[004h 0004 4] Table Length : 00000114
[008h 0008 1] Revision : 06
-[009h 0009 1] Checksum : 15
+[009h 0009 1] Checksum : 12
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] FACS Address : 00000000
[028h 0040 4] DSDT Address : 00000000
[02Ch 0044 1] Model : 00
[02Dh 0045 1] PM Profile : 00 [Unspecified]
[02Eh 0046 2] SCI Interrupt : 0000
[030h 0048 4] SMI Command Port : 00000000
[034h 0052 1] ACPI Enable Value : 00
[035h 0053 1] ACPI Disable Value : 00
[036h 0054 1] S4BIOS Command : 00
[037h 0055 1] P-State Control : 00
@@ -86,33 +86,33 @@
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 1
Low Power S0 Idle (V5) : 0
[074h 0116 12] Reset Register : [Generic Address Structure]
[074h 0116 1] Space ID : 00 [SystemMemory]
[075h 0117 1] Bit Width : 00
[076h 0118 1] Bit Offset : 00
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
[078h 0120 8] Address : 0000000000000000
[080h 0128 1] Value to cause reset : 00
[081h 0129 2] ARM Flags (decoded below) : 0003
PSCI Compliant : 1
Must use HVC for PSCI : 1
-[083h 0131 1] FADT Minor Revision : 00
+[083h 0131 1] FADT Minor Revision : 03
[084h 0132 8] FACS Address : 0000000000000000
[08Ch 0140 8] DSDT Address : 0000000000000000
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
[094h 0148 1] Space ID : 00 [SystemMemory]
[095h 0149 1] Bit Width : 00
[096h 0150 1] Bit Offset : 00
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
[098h 0152 8] Address : 0000000000000000
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
[0A0h 0160 1] Space ID : 00 [SystemMemory]
[0A1h 0161 1] Bit Width : 00
[0A2h 0162 1] Bit Offset : 00
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
[0A4h 0164 8] Address : 0000000000000000
@@ -164,34 +164,34 @@
[0F5h 0245 1] Bit Width : 00
[0F6h 0246 1] Bit Offset : 00
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
[0F8h 0248 8] Address : 0000000000000000
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
[100h 0256 1] Space ID : 00 [SystemMemory]
[101h 0257 1] Bit Width : 00
[102h 0258 1] Bit Offset : 00
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
[104h 0260 8] Address : 0000000000000000
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
Raw Table Data: Length 276 (0x114)
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
0110: 00 00 00 00 // ....
@@ -1,32 +1,32 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
*
* ACPI Data Table [GTDT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
-[004h 0004 4] Table Length : 00000060
-[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : 9C
+[004h 0004 4] Table Length : 00000068
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 93
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
[02Ch 0044 4] Reserved : 00000000
[030h 0048 4] Secure EL1 Interrupt : 0000001D
[034h 0052 4] EL1 Flags (decoded below) : 00000000
Trigger Mode : 0
Polarity : 0
Always On : 0
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
@@ -37,25 +37,28 @@
[040h 0064 4] Virtual Timer Interrupt : 0000001B
[044h 0068 4] VT Flags (decoded below) : 00000000
Trigger Mode : 0
Polarity : 0
Always On : 0
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
Trigger Mode : 0
Polarity : 0
Always On : 0
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
[058h 0088 4] Platform Timer Count : 00000000
[05Ch 0092 4] Platform Timer Offset : 00000000
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
-Raw Table Data: Length 96 (0x60)
+Raw Table Data: Length 104 (0x68)
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 // ........
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
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Peter Maydell
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6c1c2e912f |
tests/qtest/bios-tables-test: Allow changes to virt GTDT
Allow changes to the virt GTDT -- we are going to add the IRQ entry for a new timer to it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20240122143537.233498-2-peter.maydell@linaro.org |
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Peter Maydell
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83ae76cea3 |
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
We deliberately don't include qtests_npcm7xx in qtests_aarch64, because we already get the coverage of those tests via qtests_arm, and we don't want to use extra CI minutes testing them twice. In commit |
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Peter Xu
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bdb0ade663 |
tests/migration-test: Stick with gicv3 in aarch64 test
Recently we introduced cross-binary migration test. It's always wanted that migration-test uses stable guest ABI for both QEMU binaries in this case, so that both QEMU binaries will be compatible on the migration stream with the cmdline specified. Switch to a static gic version "3" rather than using version "max", so that GIC should be stable now across any future QEMU binaries for migration-test. Here the version can actually be anything as long as the ABI is stable. We choose "3" because it's the majority of what we already use in QEMU while still new enough: "git grep gic-version=3" shows 6 hit, while version 4 has no direct user yet besides "max". Note that even with this change, aarch64 won't be able to work yet with migration cross binary test, but then the only missing piece will be the stable CPU model. Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Link: https://lore.kernel.org/r/20240207005403.242235-2-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Peter Maydell
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4f2fdb10b5 |
target/arm: fix exception syndrome for AArch32 bkpt insn
pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD jGjDBz6mryWvP2H0xSmERQ== =azdP -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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David Woodhouse
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707a42e2db |
hw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliases
Also update the test to specify which device to attach the test socket to, and remove the comment lamenting the fact that we can't do so. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> |
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Nabih Estefan Diaz
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d710b33751 |
tests/qtest: Adding PCS Module test to GMAC Qtest
- Add PCS Register check to npcm_gmac-test Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12 Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-7-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Nabih Estefan Diaz
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327b680877 |
tests/qtest: Creating qtest for GMAC Module
- Created qtest to check initialization of registers in GMAC Module. - Implemented test into Build File. Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-4-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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cabe58b0f8 |
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
This test program is the last use of any variable length array in the codebase. If we can get rid of all uses of VLAs we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). In this case the test code didn't even want a variable-sized array, it was just accidentally using syntax that gave it one. (The array size for C has to be an actual constant expression, not just something that happens to be known to be constant...) Remove the VLA usage. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240125173211.1786196-2-peter.maydell@linaro.org |
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Peter Maydell
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c3709fde59 |
aspeed queue:
* Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= =0C5S -----END PGP SIGNATURE----- Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into staging aspeed queue: * Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 # 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD # lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q # 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb # 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj # wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI # yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo # ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH # 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ # 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ # 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb # D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= # =0C5S # -----END PGP SIGNATURE----- # gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu: hw/fsi: Update MAINTAINER list hw/fsi: Added FSI documentation hw/fsi: Added qtest hw/arm: Hook up FSI module in AST2600 hw/fsi: Aspeed APB2OPB & On-chip peripheral bus hw/fsi: Introduce IBM's FSI master hw/fsi: Introduce IBM's cfam hw/fsi: Introduce IBM's fsi-slave model hw/fsi: Introduce IBM's FSI Bus hw/fsi: Introduce IBM's scratchpad device hw/fsi: Introduce IBM's Local bus hw/arm/aspeed: Check for CPU types in machine_run_board_init() hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper hw/arm/aspeed: Init CPU defaults in a common helper hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() hw/arm/aspeed: Remove dead code tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Ninad Palsule
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45d8cdbd56 |
hw/fsi: Added qtest
Added basic qtests for FSI model. Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> [ clg: aspeed-fsi-test.c -> aspeed_fsi-test.c to match other filenames ] Signed-off-by: Cédric Le Goater <clg@kaod.org> |
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Peter Maydell
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00e3deef8e |
aspeed: Clean up includes
This commit was created with scripts/clean-includes. All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> |
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Paolo Bonzini
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73b4987858 |
userfaultfd: use 1ULL to build ioctl masks
There is no need to use the Linux-internal __u64 type, 1ULL is guaranteed to be wide enough. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240117160313.175609-1-pbonzini@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Thomas Huth
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4dfa7dc2ac |
tests/qtest: Bump timeouts of boot_sector_test()-based tests to 610 seconds
We're still seeing timeouts in qtests that use a TCG payload with TCI on a slow k8s runner: https://gitlab.com/qemu-project/qemu/-/jobs/5990992722 So we should bump the timeout of cdrom-test to see whether that fixes the issue. Now, cdrom-test, as bios-tables-test, pxe-test and vmgenid-test use the boot_sector_test() function for running a TCG payload. That function already uses an internal timeout of 600 seconds with the remark that the test could be slow with TCI. Thus from the outer meson test runner side, we should not use less than 600 seconds as timeout values for these tests. Let's bump them on the meson side to 610 seconds so that the tests themselves can run with their internal 600 seconds timeout and have some additional seconds on top for reporting the outcome. Message-ID: <20240124084412.465638-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Thomas Huth
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a1f5a47b60 |
tests/qtest: Bump timeout of the boot-serial-test to 360 seconds
On the slow k8s CI runner, the test sometimes takes more than 240 seconds. See for example this run here where it took ~ 267 seconds: https://gitlab.com/qemu-project/qemu/-/jobs/5806087027#L4769 Thus we have to bump the timeout here even further to be on the safe side. Let's use 360 seconds which should hopefully really be high enough now. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2097 Message-ID: <20240123110353.30658-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Philippe Mathieu-Daudé
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97b6e1d35f |
hmp: Remove deprecated 'singlestep' command
This command has been deprecated before the 8.1 release,
in commit
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Peter Maydell
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88cf5fec91 |
target-arm queue:
* docs/devel/docs: Document .hx file syntax * arm_pamax() no longer needs to do feature propagation * docs/system/arm/virt.rst: Improve 'highmem' option docs * STM32L4x5 Implement SYSCFG and EXTI devices * hw/timer: fix systick trace message * hw/arm/virt: Consolidate valid CPU types * load_elf: fix iterator's type for elf file processing -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWpHM4ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pZxD/sGIXvTeoOCsum7OFpArKoQ J+wcy74pO526IDzjudgtwP8kFW09oVblMPgrt/68F9LY4Oa7sDNAZX/Xqlhs/hdJ SVbOXArRmyLvgLpn8KVii9xk9iI/olMGt0S6KcXAErdgFud+JcCevbS0D5fAF4Ua /G/4ldnwr+WcYUA5IIoi02ymSBm5VNeH2bKu0MPS3xpizjzgOFxWTBYwq3zkZYWD w5GjH9+F+IC67CiAlCLvuQBqpGLdRwFBttU05hLtGXuSlnvS+FtJTooI7gGD17CR 2wTa7qF716qDN1lNSIvxA6t8/dWNMIYCZYdlxJml476WzP3jECpth2WFWqE0G3yg Orr7sFVB8X6JmtlR34srW6e3CZA3t+4FIWqcdELFLi5IQtJeer90jqQ9xwx4SttJ nsHdy5M8txWSa61yAaDTXMID/smVlC7sWTKJrR9kV7v5+b9OPQ/R8k0mCODl5Aer mzAVuCvUQVYK3j7fzprGrlldla57s3v78OAhqACLgKflK0+aJSJjglulPrSMK1z5 bRPS5jLZjFwEi2VaLVg3LPJiBMDj1s/wAl0ycfCQSv2oEzvmpkw+Ar1HDc2NFe+d 9dunbdhAZJMwh+ABIg7iMj+l0ncOXDa4DS+6BnjRxfECCa172u3viq1HATkLLAFI GTkcJ5hIQzNEeg9ob0MDIg== =Rfpe -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240118' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * docs/devel/docs: Document .hx file syntax * arm_pamax() no longer needs to do feature propagation * docs/system/arm/virt.rst: Improve 'highmem' option docs * STM32L4x5 Implement SYSCFG and EXTI devices * hw/timer: fix systick trace message * hw/arm/virt: Consolidate valid CPU types * load_elf: fix iterator's type for elf file processing # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWpHM4ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pZxD/sGIXvTeoOCsum7OFpArKoQ # J+wcy74pO526IDzjudgtwP8kFW09oVblMPgrt/68F9LY4Oa7sDNAZX/Xqlhs/hdJ # SVbOXArRmyLvgLpn8KVii9xk9iI/olMGt0S6KcXAErdgFud+JcCevbS0D5fAF4Ua # /G/4ldnwr+WcYUA5IIoi02ymSBm5VNeH2bKu0MPS3xpizjzgOFxWTBYwq3zkZYWD # w5GjH9+F+IC67CiAlCLvuQBqpGLdRwFBttU05hLtGXuSlnvS+FtJTooI7gGD17CR # 2wTa7qF716qDN1lNSIvxA6t8/dWNMIYCZYdlxJml476WzP3jECpth2WFWqE0G3yg # Orr7sFVB8X6JmtlR34srW6e3CZA3t+4FIWqcdELFLi5IQtJeer90jqQ9xwx4SttJ # nsHdy5M8txWSa61yAaDTXMID/smVlC7sWTKJrR9kV7v5+b9OPQ/R8k0mCODl5Aer # mzAVuCvUQVYK3j7fzprGrlldla57s3v78OAhqACLgKflK0+aJSJjglulPrSMK1z5 # bRPS5jLZjFwEi2VaLVg3LPJiBMDj1s/wAl0ycfCQSv2oEzvmpkw+Ar1HDc2NFe+d # 9dunbdhAZJMwh+ABIg7iMj+l0ncOXDa4DS+6BnjRxfECCa172u3viq1HATkLLAFI # GTkcJ5hIQzNEeg9ob0MDIg== # =Rfpe # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 Jan 2024 12:42:54 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240118' of https://git.linaro.org/people/pmaydell/qemu-arm: load_elf: fix iterator's type for elf file processing hw/arm/virt: Consolidate valid CPU types hw/timer: fix systick trace message tests/qtest: Add STM32L4x5 SYSCFG QTest testcase hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC hw/misc: Implement STM32L4x5 SYSCFG tests/qtest: Add STM32L4x5 EXTI QTest testcase hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC hw/misc: Implement STM32L4x5 EXTI docs/system/arm/virt.rst: Improve 'highmem' option docs target/arm: arm_pamax() no longer needs to do feature propagation docs/devel/docs: Document .hx file syntax Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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f94e74a7e2 |
* Improve the timeouts for some problematic qtests
* Enable some ROP mitigation compiler switches -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmWmNDURHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbVM0w/+Nafbtnw9Q1gp633CIYQRsNDGiKiCND5H epLfd3DFAG2jATZm/hIIrV3dlEkGRQh916XKik572eUm2yyu3i3EqVNooTcLr0k/ 4MI1ZzG0rnAnAr15zVdUaDCiaGdlpcSGTwLDAlQjIR4n0MdugQ/bkrfkDRU0YD/6 mv/yDck5fHOUDm88LA7Gxep0G7U8Wi8oiQXx+WlbQpmDHfBJM7ERQSPhXobtVtFO 8wpceUcMwlGBecxEsRggrRhdn09CJUyuirP8UHG4rT8xMjkXpqHJVqZ+gVDyV65J y9y6snCk+oFyCTDSstQxVbzHg/1C4xE2gVUMaXv4Wu1TcCgBpF1WDQymXb35Buuh pbgAaF1ZsBGwE7rUUJIF3NBTpjmedP4NbCR2EPsiL06w08mG7IRuU/b8JStuAHef qUqxiHfpEwAxXY8O83XOvBb+zJ625OQHGi/MGDnaYczBfqBJAx2AKiuSmMWBAWo2 gO4kQX25sPzov6xsLcjEwh0HcJ9W5mkGRJ/x8GSjWnvDlGBDBYWPUShJlohDKGU0 4+JGk4+8RKMoKE97bO8DItOp9ahh87up/qHDFkJJo+VKuDaBPdzlS6PURzc8wv0T QquWUkfdE6qYIPr8ShVYT00NNThIKLyn0qaN4s1mQ+2h8p8nXc4aYsWgcr2wxJFm sOoVvwOXzDE= =Yuwq -----END PGP SIGNATURE----- Merge tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu into staging * Improve the timeouts for some problematic qtests * Enable some ROP mitigation compiler switches # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmWmNDURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVM0w/+Nafbtnw9Q1gp633CIYQRsNDGiKiCND5H # epLfd3DFAG2jATZm/hIIrV3dlEkGRQh916XKik572eUm2yyu3i3EqVNooTcLr0k/ # 4MI1ZzG0rnAnAr15zVdUaDCiaGdlpcSGTwLDAlQjIR4n0MdugQ/bkrfkDRU0YD/6 # mv/yDck5fHOUDm88LA7Gxep0G7U8Wi8oiQXx+WlbQpmDHfBJM7ERQSPhXobtVtFO # 8wpceUcMwlGBecxEsRggrRhdn09CJUyuirP8UHG4rT8xMjkXpqHJVqZ+gVDyV65J # y9y6snCk+oFyCTDSstQxVbzHg/1C4xE2gVUMaXv4Wu1TcCgBpF1WDQymXb35Buuh # pbgAaF1ZsBGwE7rUUJIF3NBTpjmedP4NbCR2EPsiL06w08mG7IRuU/b8JStuAHef # qUqxiHfpEwAxXY8O83XOvBb+zJ625OQHGi/MGDnaYczBfqBJAx2AKiuSmMWBAWo2 # gO4kQX25sPzov6xsLcjEwh0HcJ9W5mkGRJ/x8GSjWnvDlGBDBYWPUShJlohDKGU0 # 4+JGk4+8RKMoKE97bO8DItOp9ahh87up/qHDFkJJo+VKuDaBPdzlS6PURzc8wv0T # QquWUkfdE6qYIPr8ShVYT00NNThIKLyn0qaN4s1mQ+2h8p8nXc4aYsWgcr2wxJFm # sOoVvwOXzDE= # =Yuwq # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 Jan 2024 07:45:57 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu: meson: mitigate against use of uninitialize stack for exploits meson: mitigate against ROP exploits with -fzero-call-used-regs qtest: Bump npcm7xx_watchdog_timer-test timeout to 2 minutes tests/qtest/npcm7xx_watchdog_timer: Only test the corner cases by default tests/qtest/meson.build: Bump the boot-serial-test timeout to 4 minutes Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Thomas Huth
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2d1f10229a |
qtest: Bump npcm7xx_watchdog_timer-test timeout to 2 minutes
The npcm7xx_watchdog_timer-test can take more than 60 seconds in SPEED=slow mode on a loaded host system. Bumping to 2 minutes will give more headroom. Message-ID: <20240112164717.1063954-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Thomas Huth
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d9e2da0ccc |
tests/qtest/npcm7xx_watchdog_timer: Only test the corner cases by default
The test_prescaler() part in the npcm7xx_watchdog_timer test is quite repetitive, testing all possible combinations of the WTCLK and WTIS bitfields. Since each test spins up a new instance of QEMU, this is rather an expensive test, especially on loaded host systems. For the normal quick test mode, it should be sufficient to test the corner settings of these fields (i.e. 0 and 3), so we can speed up this test in the default mode quite a bit. Message-ID: <20240115070223.30178-1-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Thomas Huth
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cfae053704 |
tests/qtest/meson.build: Bump the boot-serial-test timeout to 4 minutes
When running with TCI, the boot-serial-test can take longer than 3 minutes: https://gitlab.com/qemu-project/qemu/-/jobs/5890481086#L4774 Bump the timeout to 4 minutes to avoid CI failures here. Message-ID: <20240115071146.31213-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Fabiano Rosas
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75b1f88cd2 |
tests/qtest: Re-enable multifd cancel test
We've found the source of flakiness in this test, so re-enable it. Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20230606144551.24367-4-farosas@suse.de [peterx: rebase to 2a61a6964c, to use migration_test_add()] Signed-off-by: Peter Xu <peterx@redhat.com> |
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Fabiano Rosas
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6f0771de90 |
tests/qtest/migration: Use the new migration_test_add
Replace the tests registration with the new function that prints tests names. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240104142144.9680-8-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
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Fabiano Rosas
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e33b6712db |
tests/qtest/migration: Add a wrapper to print test names
Our usage of gtest results in us losing the very basic functionality
of "knowing which test failed". The issue is that gtest only prints
test names ("paths" in gtest parlance) once the test has finished, but
we use asserts in the tests and crash gtest itself before it can print
anything. We also use a final abort when the result of g_test_run is
not 0.
Depending on how the test failed/broke we can see the function that
trigged the abort, which may be representative of the test, but it
could also just be some generic function.
We have been relying on the primitive method of looking at the name of
the previous successful test and then looking at the code to figure
out which test should have come next.
Add a wrapper to the test registration that does the job of printing
the test name before running.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Peter Xu <peterx@redhat.com>
Link: https://lore.kernel.org/r/20240104142144.9680-7-farosas@suse.de
Signed-off-by: Peter Xu <peterx@redhat.com>
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Fabiano Rosas
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679a7382a3 |
tests/qtest/migration: Print migration incoming errors
We're currently just asserting when incoming migration fails. Let's print the error message from QMP as well. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240104142144.9680-6-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com> |
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Inès Varhol
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a96bff6157 |
tests/qtest: Add STM32L4x5 SYSCFG QTest testcase
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240109194438.70934-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Inès Varhol
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4cb445717e |
tests/qtest: Add STM32L4x5 EXTI QTest testcase
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240109160658.311932-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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977542ded7 |
testing and misc updates
- add LE microblaze test to avocado - use modern snapshot=on to avoid trashing disk image - use plain bool for fe_is_open - various updates to qtest timeouts - enable meson test timeouts - tweak the readthedocs environment - partially revert un-flaking x86_64 -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmWhPccACgkQ+9DbCVqe KkS5agf+OoW6HOitt34YeL6cGGtIKaxbta+Fs6jq+ucIbN63TmLTuKrmPiRNxjuo Fj2Qvh9R7Tl7Q/a7ZAym0Fze7GtsvvsidkiQS4pmi9vYuJrhS734CxXHT8JS6zJr ymQ0nGZODg1cVB4oAR9sXo/OwEQdDTSgKp8wdNr930fxYwokUKBUgcOqElu3SWHv duSYDuaflnP5B8ZGbb1ZnOlwS9lZIHTwjZyN5J1YtxF0T8Ez4A+xseEOpQ/00MoE Ecjdp3ELCxzOI+1U33Yni7ol//fxQpRKi+xf2fGIxhuSA3i32rmY5NWTvl7VwuS1 gXryjX2rukSujySP3vkdtTp0dmkbpg== =ZuDd -----END PGP SIGNATURE----- Merge tag 'pull-testing-updates-120124-2' of https://gitlab.com/stsquad/qemu into staging testing and misc updates - add LE microblaze test to avocado - use modern snapshot=on to avoid trashing disk image - use plain bool for fe_is_open - various updates to qtest timeouts - enable meson test timeouts - tweak the readthedocs environment - partially revert un-flaking x86_64 # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmWhPccACgkQ+9DbCVqe # KkS5agf+OoW6HOitt34YeL6cGGtIKaxbta+Fs6jq+ucIbN63TmLTuKrmPiRNxjuo # Fj2Qvh9R7Tl7Q/a7ZAym0Fze7GtsvvsidkiQS4pmi9vYuJrhS734CxXHT8JS6zJr # ymQ0nGZODg1cVB4oAR9sXo/OwEQdDTSgKp8wdNr930fxYwokUKBUgcOqElu3SWHv # duSYDuaflnP5B8ZGbb1ZnOlwS9lZIHTwjZyN5J1YtxF0T8Ez4A+xseEOpQ/00MoE # Ecjdp3ELCxzOI+1U33Yni7ol//fxQpRKi+xf2fGIxhuSA3i32rmY5NWTvl7VwuS1 # gXryjX2rukSujySP3vkdtTp0dmkbpg== # =ZuDd # -----END PGP SIGNATURE----- # gpg: Signature made Fri 12 Jan 2024 13:25:27 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-testing-updates-120124-2' of https://gitlab.com/stsquad/qemu: (22 commits) tests/avocado: partially revert unmasking of replay_linux tests readthodocs: fully specify a build environment mtest2make: stop disabling meson test timeouts tests/fp: Bump fp-test-mulAdd test timeout to 3 minutes tests/unit: Bump test-crypto-block test timeout to 5 minutes tests/unit: Bump test-aio-multithread test timeout to 2 minutes tests/qtest: Bump the device-introspect-test timeout to 12 minutes qtest: bump bios-table-test timeout to 9 minutes qtest: bump aspeed_smc-test timeout to 6 minutes qtest: bump qos-test timeout to 2 minutes qtest: bump boot-serial-test timeout to 3 minutes qtest: bump prom-env-test timeout to 6 minutes qtest: bump pxe-test timeout to 10 minutes qtest: bump test-hmp timeout to 4 minutes qtest: bump npcm7xx_pwm-test timeout to 5 minutes qtest: bump qom-test timeout to 15 minutes qtest: bump migration-test timeout to 8 minutes qtest: bump min meson timeout to 60 seconds chardev: use bool for fe_is_open gitlab: include microblazeel in testing ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Thomas Huth
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50dfa7ca48 |
tests/qtest: Bump the device-introspect-test timeout to 12 minutes
When running the test in slow mode on a very loaded system with the arm/aarch64 target and with --enable-debug, it can take longer than 10 minutes to finish the introspection test. Bump the timeout to twelve minutes to make sure that it also finishes in such situations. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-13-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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794876fb52 |
qtest: bump bios-table-test timeout to 9 minutes
This is reliably hitting the current 2 minute timeout in GitLab CI, and for the TCI job, it even hits a 6 minute timeout. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-12-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-12-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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e8a12fe31f |
qtest: bump aspeed_smc-test timeout to 6 minutes
On a loaded system with --enable-debug, this test can take longer than 5 minutes. Raising the timeout to 6 minutes gives greater headroom for such situations. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> [thuth: Increase the timeout to 6 minutes for very loaded systems] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-11-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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f6bee9c2f2 |
qtest: bump qos-test timeout to 2 minutes
The qos-test takes just under 1 minute in a --enable-debug build. Bumping to 2 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-10-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-10-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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93b6d67348 |
qtest: bump boot-serial-test timeout to 3 minutes
The boot-serial-test takes about 1 + 1/2 minutes in a --enable-debug build. Bumping to 3 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-9-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-9-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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8911563900 |
qtest: bump prom-env-test timeout to 6 minutes
The prom-env-test can take more than 5 minutes in a --enable-debug build on a loaded system. Bumping to 6 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> [thuth: Bump timeout to 6 minutes instead of 3] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-8-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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17e164da12 |
qtest: bump pxe-test timeout to 10 minutes
The pxe-test uses the boot_sector_test() function, and that already uses a timeout of 600 seconds. So adjust the timeout on the meson side accordingly. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> [thuth: Bump timeout to 600s and adjust commit description] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-7-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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f6d8d0e542 |
qtest: bump test-hmp timeout to 4 minutes
The hmp test takes just under 3 minutes in a --enable-debug build. Bumping to 4 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-6-berrange@redhat.com> [thuth: fix copy-n-paste error in the description] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-6-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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d05328bcb0 |
qtest: bump npcm7xx_pwm-test timeout to 5 minutes
The npcm7xx_pwm-test takes 3 & 1/2 minutes in a --enable-debug build. Bumping to 5 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-5-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-5-thuth@redhat.com> [AJB: s/pwn/pwm] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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cb2218ab16 |
qtest: bump qom-test timeout to 15 minutes
The qom-test is periodically hitting the 5 minute timeout when running on the aarch64 emulator under GitLab CI. With an --enable-debug build it can take over 10 minutes for arm/aarch64 targets. Setting timeout to 15 minutes gives enough headroom to hopefully make it reliable. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-4-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-4-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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7071795114 |
qtest: bump migration-test timeout to 8 minutes
The migration test should take between 1 min 30 and 2 mins on reasonably modern hardware. The test is not especially compute bound, rather its running time is dominated by the guest RAM size relative to the bandwidth cap, which forces each iteration to take at least 30 seconds. None the less under high load conditions with multiple QEMU processes spawned and competing with other parallel tests, the worst case running time might be somewhat extended. Bumping the timeout to 8 minutes gives us good headroom, while still catching stuck tests relatively quickly. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-3-berrange@redhat.com> [thuth: Bump timeout to 8 minutes to make it work on very loaded systems, too] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-3-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Daniel P. Berrangé
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9eb95e5c56 |
qtest: bump min meson timeout to 60 seconds
Even some of the relatively fast qtests can sometimes hit the 30 second timeout in GitLab CI under high parallelism/load conditions. Bump the min to 60 seconds to give a higher margin for reliability. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-2-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-2-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
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Samuel Tardieu
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c98873ee4a |
tests/qtest/virtio-ccw: Fix device presence checking
An apparent copy-paste error tests for the presence of the
virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw
device.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Message-ID: <20240106130121.1244993-1-sam@rfc1149.net>
Fixes:
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Daniel P. Berrangé
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f51d3fb14d |
qtest: ensure netdev-socket tests have non-overlapping names
When naming glib tests if the name of one test is a substring of the name of another test, it is not possible to use the '-p /the/name' option to run a single test. Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240104162942.211458-7-berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Daniel P. Berrangé
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cc91ca64d8 |
net: add explicit info about connecting/listening state
When running 'info network', if the stream backend is still in the process of connecting, or waiting for an incoming connection, no information is displayed. There is also no way to distinguish whether the server is still in the process of setting up the listener socket, or whether it is ready to accept incoming client connections. This leads to a race condition in the netdev-socket qtest which launches a server process followed by a client process. Under high load conditions it is possible for the client to attempt to connect before the server is accepting clients. For the scenarios which do not set the 'reconnect' option, this opens up a race which can lead to the test scenario failing to reach the expected state. Now that 'info network' can distinguish between initialization phase and the listening phase, the netdev-socket qtest will correctly synchronize, such that the client QEMU is not spawned until the server is ready. This should solve the non-deterministic failures seen with the netdev-socket qtest. Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240104162942.211458-5-berrange@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Daniel P. Berrangé
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a298293866 |
Revert "tests/qtest/netdev-socket: Raise connection timeout to 120 seconds"
This reverts commit
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Daniel P. Berrangé
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9f7ac8e869 |
Revert "netdev: set timeout depending on loadavg"
This reverts commit
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Daniel P. Berrangé
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b01932889d |
qtest: use correct boolean type for failover property
QMP device_add does not historically validate the parameter types. At some point it will likely change to enforce correct types, to match behaviour of -device. The failover property is expected to be a boolean in JSON. Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240103123005.2400437-1-berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Peter Maydell
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c8193acc07 |
migration 1st pull for 9.0
- We lost Juan and Leo in the maintainers file - Steven's suspend state fix - Steven's fix for coverity on migrate_mode - Avihai's migration cleanup series -----BEGIN PGP SIGNATURE----- iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZZY0TxIccGV0ZXJ4QHJl ZGhhdC5jb20ACgkQO1/MzfOr1wbSxgEAoM5g3wkc22lpAlRpU+hJUqT9NVOVQSK+ Fk7XJYTdSgABAKzykA6hAmU5Kj+yVI6jI874SVZbs2FWpFs4osvsKk4D =sfuM -----END PGP SIGNATURE----- Merge tag 'migration-20240104-pull-request' of https://gitlab.com/peterx/qemu into staging migration 1st pull for 9.0 - We lost Juan and Leo in the maintainers file - Steven's suspend state fix - Steven's fix for coverity on migrate_mode - Avihai's migration cleanup series # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZZY0TxIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wbSxgEAoM5g3wkc22lpAlRpU+hJUqT9NVOVQSK+ # Fk7XJYTdSgABAKzykA6hAmU5Kj+yVI6jI874SVZbs2FWpFs4osvsKk4D # =sfuM # -----END PGP SIGNATURE----- # gpg: Signature made Thu 04 Jan 2024 04:30:07 GMT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [unknown] # gpg: aka "Peter Xu <peterx@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'migration-20240104-pull-request' of https://gitlab.com/peterx/qemu: (26 commits) migration: fix coverity migrate_mode finding migration/multifd: Remove unnecessary usage of local Error migration: Remove unnecessary usage of local Error migration: Fix migration_channel_read_peek() error path migration/multifd: Remove error_setg() in migration_ioc_process_incoming() migration/multifd: Fix leaking of Error in TLS error flow migration/multifd: Simplify multifd_channel_connect() if else statement migration/multifd: Fix error message in multifd_recv_initial_packet() migration: Remove errp parameter in migration_fd_process_incoming() migration: Refactor migration_incoming_setup() migration: Remove nulling of hostname in migrate_init() migration: Remove migrate_max_downtime() declaration tests/qtest: postcopy migration with suspend tests/qtest: precopy migration with suspend tests/qtest: option to suspend during migration tests/qtest: migration events migration: preserve suspended for bg_migration migration: preserve suspended for snapshot migration: preserve suspended runstate migration: propagate suspended runstate ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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05470c3979 |
* configure: use a native non-cross compiler for linux-user
* meson: cleanups * target/i386: miscellaneous cleanups and optimizations * target/i386: implement CMPccXADD * target/i386: the sgx_epc_get_section stub is reachable * esp: check for NULL result from scsi_device_find() -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmWRImYUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNd7AgAgcyJGiMfUkXqhefplpm06RDXQIa8 FuoJqPb21lO75DQKfaFRAc4xGLagjJROMJGHMm9HvMu2VlwvOydkQlfFRspENxQ/ 5XzGdb/X0A7HA/mwUfnMB1AZx0Vs32VI5IBSc6acc9fmgeZ84XQEoM3KBQHUik7X mSkE4eltR9gJ+4IaGo4voZtK+YoVD8nEcuqmnKihSPWizev0FsZ49aNMtaYa9qC/ Xs3kiQd/zPibHDHJu0ulFsNZgxtUcvlLHTCf8gO4dHWxCFLXGubMush83McpRtNB Qoh6cTLH+PBXfrxMR3zmTZMNvo8Euls3s07Y8TkNP4vdIIE/kMeMDW1wJw== =mq30 -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * configure: use a native non-cross compiler for linux-user * meson: cleanups * target/i386: miscellaneous cleanups and optimizations * target/i386: implement CMPccXADD * target/i386: the sgx_epc_get_section stub is reachable * esp: check for NULL result from scsi_device_find() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmWRImYUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNd7AgAgcyJGiMfUkXqhefplpm06RDXQIa8 # FuoJqPb21lO75DQKfaFRAc4xGLagjJROMJGHMm9HvMu2VlwvOydkQlfFRspENxQ/ # 5XzGdb/X0A7HA/mwUfnMB1AZx0Vs32VI5IBSc6acc9fmgeZ84XQEoM3KBQHUik7X # mSkE4eltR9gJ+4IaGo4voZtK+YoVD8nEcuqmnKihSPWizev0FsZ49aNMtaYa9qC/ # Xs3kiQd/zPibHDHJu0ulFsNZgxtUcvlLHTCf8gO4dHWxCFLXGubMush83McpRtNB # Qoh6cTLH+PBXfrxMR3zmTZMNvo8Euls3s07Y8TkNP4vdIIE/kMeMDW1wJw== # =mq30 # -----END PGP SIGNATURE----- # gpg: Signature made Sun 31 Dec 2023 08:12:22 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (46 commits) meson.build: report graphics backends separately configure, meson: rename targetos to host_os meson: rename config_all meson: remove CONFIG_ALL meson: remove config_targetos meson: remove CONFIG_POSIX and CONFIG_WIN32 from config_targetos meson: remove OS definitions from config_targetos meson: always probe u2f and canokey if the option is enabled meson: move subdirs to "Collect sources" section meson: move config-host.h definitions together meson: move CFI detection code with other compiler flags meson: keep subprojects together meson: move accelerator dependency checks together meson: move option validation together meson: move program checks together meson: add more sections to main meson.build configure: unify again the case arms in probe_target_compiler configure: remove unnecessary subshell Makefile: clean qemu-iotests output meson: use version_compare() to compare version ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Steve Sistare
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2b58a8b963 |
tests/qtest: postcopy migration with suspend
Add a test case to verify that the suspended state is handled correctly by live migration postcopy. The test suspends the src, migrates, then wakes the dest. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/1704312341-66640-13-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Steve Sistare
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b1fdd21e8c |
tests/qtest: precopy migration with suspend
Add a test case to verify that the suspended state is handled correctly during live migration precopy. The test suspends the src, migrates, then wakes the dest. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/1704312341-66640-12-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Steve Sistare
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5014478e0d |
tests/qtest: option to suspend during migration
Add an option to suspend the src in a-b-bootblock.S, which puts the guest in S3 state after one round of writing to memory. The option is enabled by poking a 1 into the suspend_me word in the boot block prior to starting the src vm. Generate symbol offsets in a-b-bootblock.h so that the suspend_me offset is known. Generate the bootblock for each test, because suspend_me may differ for each. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/1704312341-66640-11-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Steve Sistare
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f0649758be |
tests/qtest: migration events
Define a state object to capture events seen by migration tests, to allow more events to be captured in a subsequent patch, and simplify event checking in wait_for_migration_pass. No functional change. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Link: https://lore.kernel.org/r/1704312341-66640-10-git-send-email-steven.sistare@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com> |
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Paolo Bonzini
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d0cda6f461 |
configure, meson: rename targetos to host_os
This variable is about the host OS, not the target. It is used a lot more since the Meson conversion, but the original sin dates back to 2003. Time to fix it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Paolo Bonzini
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cfc1a889e5 |
meson: rename config_all
config_all now lists only accelerators, rename it to indicate its actual content. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Paolo Bonzini
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1220f5813a |
meson: remove config_targetos
config_targetos is now empty and can be removed; its use in sourcesets that do not involve target-specific files can be replaced with an empty dictionary. In fact, at this point *all* sourcesets that do not involve target-specific files are just glorified mutable arrays. Enforce that they never test for symbols in "when:" by computing the set of files without "strict: false". Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Zhao Liu
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c40db4ba60 |
tests: bios-tables-test: Rename smbios type 4 related test functions
In fact, type4-count, core-count, core-count2, thread-count and thread-count2 are tested with KVM not TCG. Rename these test functions to reflect KVM base instead of TCG. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231127160202.1037290-1-zhao1.liu@linux.intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Thomas Huth
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71dc6ca2a8 |
tests/qtest/npcm7xx_pwm-test: Only do full testing in slow mode
The npcm7xx_pwm-test can take quite a while when running with --enable-debug on a loaded system. The tests here are quite repetitive - by default it should be fine if we only execute some of them and only execute all when running in slow testing mode. Message-ID: <20231215143524.49241-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Thomas Huth
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81c2c9dd5d |
tests/qtest/migration-test: Fix analyze-migration.py for s390x
The migration stream on s390x contains data for the storage_attributes which the analyze-migration.py cannot handle yet. Add the basic code for handling this, so we can re-enable the check in the migration-test. Message-ID: <20231120113951.162090-1-thuth@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Stefan Hajnoczi
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169c4e7764 |
* Fix wording in iotest 149
* Fix whitespace issues in sh4 code (ignore checkpatch.pl warnings here) * Make sure to check return values in qtests -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVt4PwRHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbWhYxAAm6ww++qfCh5uLrKjXrv/ZS+b+8UVMT+p wOBNBz0RDpDahAwesxLABAg9b+fabLTx9OpOyQRgmM/ofCoW/Oi7xzCEwv9JPJX0 Kr7x5AMCTc2hPydxsMenWYZXLZXcc0HSkB+4yN5FTeOl8YPoRetegsGbiirGpod1 QyD/oLMZzBxqteF/m0a4gxEuwi3qgRVIOkdk8zeSBMAl6EUazsKR8sTrdCrkupHl ddMKjRH4Gr2sXoZ8L/mr4T5FodVxAF1pcZnVyPYDlVgNK/V0IWDcbmFFNr0rXxCM CZz7gIOZkpm/MXpVE9UEg++ZOQ16gDUNpvQRyNPgIn0vbiuF5kcXmUpstJWHDico O98wgH6im3iC7xyaMTOq3pjSb9RNP4cmIw77EKJyS93RDAgiCX0ozN3zEkxsvZYu hQadBd3TSUP6jxz2SWQ6irCwkElfozCc1cPfUyW0rFXjLqWei0UirWDdyN5dL8vk pkupZG5p3jiiZs1hm+TQ4W1CPVZFTAW+LcI7V/Na3EBKQvrjYDlHMQdx0NaJh5e3 xn84bvTnuYfT/I63z9zqIbMwPQ5t+lJaR9ohkn9Q4tTEnHuMV9svON5rsRc3YE6p XrR02G9zu4kVAKs51DFNWC9SLgviW+LB2DCe+e2CrqwPjiz+MeOVGEEre7/nnj/q clP7u3MyX5A= =rU6S -----END PGP SIGNATURE----- Merge tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu into staging * Fix wording in iotest 149 * Fix whitespace issues in sh4 code (ignore checkpatch.pl warnings here) * Make sure to check return values in qtests # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVt4PwRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWhYxAAm6ww++qfCh5uLrKjXrv/ZS+b+8UVMT+p # wOBNBz0RDpDahAwesxLABAg9b+fabLTx9OpOyQRgmM/ofCoW/Oi7xzCEwv9JPJX0 # Kr7x5AMCTc2hPydxsMenWYZXLZXcc0HSkB+4yN5FTeOl8YPoRetegsGbiirGpod1 # QyD/oLMZzBxqteF/m0a4gxEuwi3qgRVIOkdk8zeSBMAl6EUazsKR8sTrdCrkupHl # ddMKjRH4Gr2sXoZ8L/mr4T5FodVxAF1pcZnVyPYDlVgNK/V0IWDcbmFFNr0rXxCM # CZz7gIOZkpm/MXpVE9UEg++ZOQ16gDUNpvQRyNPgIn0vbiuF5kcXmUpstJWHDico # O98wgH6im3iC7xyaMTOq3pjSb9RNP4cmIw77EKJyS93RDAgiCX0ozN3zEkxsvZYu # hQadBd3TSUP6jxz2SWQ6irCwkElfozCc1cPfUyW0rFXjLqWei0UirWDdyN5dL8vk # pkupZG5p3jiiZs1hm+TQ4W1CPVZFTAW+LcI7V/Na3EBKQvrjYDlHMQdx0NaJh5e3 # xn84bvTnuYfT/I63z9zqIbMwPQ5t+lJaR9ohkn9Q4tTEnHuMV9svON5rsRc3YE6p # XrR02G9zu4kVAKs51DFNWC9SLgviW+LB2DCe+e2CrqwPjiz+MeOVGEEre7/nnj/q # clP7u3MyX5A= # =rU6S # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Dec 2023 09:23:56 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu: tests/qtest: check the return value sh4: Coding style: Remove tabs tests/qemu-iotests/149: Use more inclusive language in this test Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> |
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Zhu Jun
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4d98618b8a |
tests/qtest: check the return value
These variables "ret" are never referenced in the code, thus add check logic for the "ret" Signed-off-by: Zhu Jun <zhujun2@cmss.chinamobile.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231121080802.4500-1-zhujun2@cmss.chinamobile.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Ani Sinha
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de35244e99 |
tests/acpi/bios-tables-test: do not write new blobs unless there are changes
When dumping table blobs using rebuild-expected-aml.sh, table blobs from all test variants are dumped regardless of whether there are any actual changes to the tables or not. This creates lot of new files for various test variants that are not part of the git repository. This is because we do not check in all table blobs for all test variants into the repository. Only those blobs for those variants that are different from the generic test-variant agnostic blob are checked in. This change makes the test smarter by checking if at all there are any changes in the tables from the checked-in gold master blobs and take actions accordingly. When there are no changes: - No new table blobs would be written. - Existing table blobs will be refreshed (git diff will show no changes). When there are changes: - New table blob files will be dumped. - Existing table blobs will be refreshed (git diff will show that the files changed, asl diff will show the actual changes). When new tables are introduced: - Zero byte empty file blobs for new tables as instructed in the header of bios-tables-test.c will be regenerated to actual table blobs. This would make analyzing changes to tables less confusing and there would be no need to clean useless untracked files when there are no table changes. CC: peter.maydell@linaro.org Signed-off-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20231107044952.5461-1-anisinha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> |
|
|
Michael S. Tsirkin
|
cadfc72939 |
netdev: set timeout depending on loadavg
netdev test keeps failing sometimes. I don't think we should increase the timeout some more: let's try something else instead, testing how busy the system is. Seems to work for me. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Michael Tokarev
|
4b3e4d2b43 |
tests/qtest/ufs-test.c: spelling fix: tranfer
Fixes:
|
|
|
Michael Tokarev
|
8053feaae0 |
tests/qtest/migration-test.c: spelling fix: bandwith
Fixes:
|
|
|
Stefan Hajnoczi
|
ed1d873caa |
Misc hardware patch queue
HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= =OVdQ -----END PGP SIGNATURE----- Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging Misc hardware patch queue HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t # wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S # vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q # jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi # zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh # ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan # DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM # L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu # DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z # HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY # Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp # 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= # =OVdQ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits) dump: Add close fd on error return to avoid resource leak ui/sdl2: use correct key names in win title on mac MAINTAINERS: Add more guest-agent related files to the corresponding section MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section MAINTAINERS: update libvirt devel mailing list address MAINTAINERS: Add the CAN documentation file to the CAN section MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section hw/sd: Declare QOM types using DEFINE_TYPES() macro hw/i2c: pmbus: reset page register for out of range reads hw/i2c: pmbus: immediately clear faults on request tests/qtest: add tests for ADM1266 hw/sensor: add ADM1266 device model hw/i2c: pmbus: add VCAP register hw/i2c: pmbus: add fan support hw/i2c: pmbus: add vout mode bitfields hw/i2c: pmbus add support for block receive tests/qtest: ahci-test: add test exposing reset issue with pending callback hw/ide: reset: cancel async DMA operation before resetting state hw/cpu: Update the comments of nr_cores and nr_dies system/cpus: Fix CPUState.nr_cores' calculation ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> |
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Titus Rwantare
|
ff0511282d |
hw/i2c: pmbus: reset page register for out of range reads
The linux pmbus driver scans all possible pages and does not reset the current page after the scan, making all future page reads fail as out of range on devices with a single page. This change resets out of range pages immediately on write. Also added a qtest for simultaneous writes to all pages. Reviewed-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-8-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
|
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Titus Rwantare
|
5861f5abf4 |
tests/qtest: add tests for ADM1266
The ADM1266 can have string fields written by the driver, so it's worth specifically testing. Reviewed-by: Hao Wu <wuhaotsh@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> [PMD: Cover file in MAINTAINERS] Message-ID: <20231023-staging-pmbus-v3-v4-6-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
|
|
Fiona Ebner
|
cc610857bb |
tests/qtest: ahci-test: add test exposing reset issue with pending callback
Before commit "hw/ide: reset: cancel async DMA operation before resetting state", this test would fail, because a reset with a pending write operation would lead to an unsolicited write to the first sector of the disk. The test writes a pattern to the beginning of the disk and verifies that it is still intact after a reset with a pending operation. It also checks that the pending operation actually completes correctly. Signed-off-by: Fiona Ebner <f.ebner@proxmox.com> Message-ID: <20230906130922.142845-2-f.ebner@proxmox.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
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Stefan Hajnoczi
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f6b615b52d |
virtio,pc,pci: features, fixes
virtio sound card support
vhost-user: back-end state migration
cxl:
line length reduction
enabling fabric management
vhost-vdpa:
shadow virtqueue hash calculation Support
shadow virtqueue RSS Support
tests:
CPU topology related smbios test cases
Fixes, cleanups all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-----BEGIN PGP SIGNATURE-----
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, fixes
virtio sound card support
vhost-user: back-end state migration
cxl:
line length reduction
enabling fabric management
vhost-vdpa:
shadow virtqueue hash calculation Support
shadow virtqueue RSS Support
tests:
CPU topology related smbios test cases
Fixes, cleanups all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# -----BEGIN PGP SIGNATURE-----
#
# iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmVKDDoPHG1zdEByZWRo
# YXQuY29tAAoJECgfDbjSjVRpF08H/0Zts8uvkHbgiOEJw4JMHU6/VaCipfIYsp01
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# 0w4IXEJPBgZYbX9oc6zvTQnbLDBJbDU89mnme0TcmNMKWmQKTtc=
# =vEv+
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Nov 2023 18:06:50 HKT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (63 commits)
acpi/tests/avocado/bits: enable console logging from bits VM
acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point
hw/cxl: Add tunneled command support to mailbox for switch cci.
hw/cxl: Add dummy security state get
hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions
hw/cxl/mbox: Add Get Background Operation Status Command
hw/cxl: Add support for device sanitation
hw/cxl/mbox: Wire up interrupts for background completion
hw/cxl/mbox: Add support for background operations
hw/cxl: Implement Physical Ports status retrieval
hw/pci-bridge/cxl_downstream: Set default link width and link speed
hw/cxl/mbox: Add Physical Switch Identify command.
hw/cxl/mbox: Add Information and Status / Identify command
hw/cxl: Add a switch mailbox CCI function
hw/pci-bridge/cxl_upstream: Move defintion of device to header.
hw/cxl/mbox: Generalize the CCI command processing
hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState
hw/cxl/mbox: Split mailbox command payload into separate input and output
hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant
hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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Zhao Liu
|
f58db4eeb1 |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-CNE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-WKE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000CA6
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
+[435h 1077 1] Length : 08
+[436h 1078 1] Processor ID : 81
+[437h 1079 1] Local Apic ID : 81
+[438h 1080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
[snip]
+[C4Ch 3148 1] Subtable Type : 09 [Processor Local x2APIC]
+[C4Dh 3149 1] Length : 10
+[C4Eh 3150 2] Reserved : 0000
+[C50h 3152 4] Processor x2Apic ID : 00000181
+[C54h 3156 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[C58h 3160 4] Processor UID : 00000103
+
+[C5Ch 3164 1] Subtable Type : 01 [I/O APIC]
+[C5Dh 3165 1] Length : 0C
+[C5Eh 3166 1] I/O Apic ID : 00
+[C5Fh 3167 1] Reserved : 00
+[C60h 3168 4] Address : FEC00000
+[C64h 3172 4] Interrupt : 00000000
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
[snip]
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-CDE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x000083EA (33770)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x01
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x81))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x81)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x81, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231023094635.1588282-17-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Zhao Liu
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198eee0cc1 |
tests: bios-tables-test: Add test for smbios type4 thread count2
This tests the commit
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Zhao Liu
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7cb953ca19 |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count2 field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-15-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Zhao Liu
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a775cb191e |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 63
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-14-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Zhao Liu
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7ee18dcef1 |
tests: bios-tables-test: Add test for smbios type4 thread count
This tests the commit
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Zhao Liu
|
85ccbe1275 |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-12-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Zhao Liu
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f03359a85b |
tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
-[004h 0004 4] Table Length : 000009AE
+[004h 0004 4] Table Length : 00000CA6
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : CE
+[009h 0009 1] Checksum : FA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
@@ -1051,1256 +1051,1136 @@
[42Ch 1068 1] Subtable Type : 00 [Processor Local APIC]
[42Dh 1069 1] Length : 08
[42Eh 1070 1] Processor ID : 80
[42Fh 1071 1] Local Apic ID : 80
[430h 1072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
[435h 1077 1] Length : 08
[436h 1078 1] Processor ID : 81
[437h 1079 1] Local Apic ID : 81
[438h 1080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
-[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC]
-[43Dh 1085 1] Length : 08
-[43Eh 1086 1] Processor ID : 82
-[43Fh 1087 1] Local Apic ID : 82
-[440h 1088 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
-
-[444h 1092 1] Subtable Type : 00 [Processor Local APIC]
-[445h 1093 1] Length : 08
-[446h 1094 1] Processor ID : 83
-[447h 1095 1] Local Apic ID : 83
-[448h 1096 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
[snip]
-
-[964h 2404 1] Subtable Type : 01 [I/O APIC]
-[965h 2405 1] Length : 0C
-[966h 2406 1] I/O Apic ID : 00
-[967h 2407 1] Reserved : 00
-[968h 2408 4] Address : FEC00000
-[96Ch 2412 4] Interrupt : 00000000
-
-[970h 2416 1] Subtable Type : 02 [Interrupt Source Override]
-[971h 2417 1] Length : 0A
-[972h 2418 1] Bus : 00
-[973h 2419 1] Source : 00
-[974h 2420 4] Interrupt : 00000002
-[978h 2424 2] Flags (decoded below) : 0000
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
+
+[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC]
+[44Dh 1101 1] Length : 10
+[44Eh 1102 2] Reserved : 0000
+[450h 1104 4] Processor x2Apic ID : 00000101
+[454h 1108 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[458h 1112 4] Processor UID : 00000083
+
[snip]
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override]
-[97Bh 2427 1] Length : 0A
-[97Ch 2428 1] Bus : 00
-[97Dh 2429 1] Source : 05
-[97Eh 2430 4] Interrupt : 00000005
-[982h 2434 2] Flags (decoded below) : 000D
+[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override]
+[C73h 3187 1] Length : 0A
+[C74h 3188 1] Bus : 00
+[C75h 3189 1] Source : 05
+[C76h 3190 4] Interrupt : 00000005
+[C7Ah 3194 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[984h 2436 1] Subtable Type : 02 [Interrupt Source Override]
-[985h 2437 1] Length : 0A
-[986h 2438 1] Bus : 00
-[987h 2439 1] Source : 09
-[988h 2440 4] Interrupt : 00000009
-[98Ch 2444 2] Flags (decoded below) : 000D
+[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override]
+[C7Dh 3197 1] Length : 0A
+[C7Eh 3198 1] Bus : 00
+[C7Fh 3199 1] Source : 09
+[C80h 3200 4] Interrupt : 00000009
+[C84h 3204 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override]
-[98Fh 2447 1] Length : 0A
-[990h 2448 1] Bus : 00
-[991h 2449 1] Source : 0A
-[992h 2450 4] Interrupt : 0000000A
-[996h 2454 2] Flags (decoded below) : 000D
+[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override]
+[C87h 3207 1] Length : 0A
+[C88h 3208 1] Bus : 00
+[C89h 3209 1] Source : 0A
+[C8Ah 3210 4] Interrupt : 0000000A
+[C8Eh 3214 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[998h 2456 1] Subtable Type : 02 [Interrupt Source Override]
-[999h 2457 1] Length : 0A
-[99Ah 2458 1] Bus : 00
-[99Bh 2459 1] Source : 0B
-[99Ch 2460 4] Interrupt : 0000000B
-[9A0h 2464 2] Flags (decoded below) : 000D
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI]
-[9A3h 2467 1] Length : 0C
-[9A4h 2468 2] Flags (decoded below) : 0000
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[9A6h 2470 4] Processor UID : FFFFFFFF
-[9AAh 2474 1] Interrupt Input LINT : 01
-[9ABh 2475 3] Reserved : 000000
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00007EEF (32495)
+ * Length 0x000083EA (33770)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x52
+ * Checksum 0x01
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\)
{
OperationRegion (DBG, SystemIO, 0x0402, One)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DBGB, 8
}
@@ -4196,107 +4196,32 @@
}
If ((Arg0 == 0x0101))
{
Notify (C101, Arg1)
}
If ((Arg0 == 0x0102))
{
Notify (C102, Arg1)
}
If ((Arg0 == 0x0103))
{
Notify (C103, Arg1)
}
-
- If ((Arg0 == 0x0104))
- {
- Notify (C104, Arg1)
- }
-
- If ((Arg0 == 0x0105))
- {
- Notify (C105, Arg1)
- }
-
- If ((Arg0 == 0x0106))
- {
- Notify (C106, Arg1)
- }
-
[snip]
- If ((Arg0 == 0x0112))
- {
- Notify (C112, Arg1)
- }
}
Method (CSTA, 1, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
If ((\_SB.PCI0.PRES.CPEN == One))
{
Local0 = 0x0F
}
Release (\_SB.PCI0.PRES.CPLK)
Return (Local0)
}
@@ -4306,33 +4231,33 @@
\_SB.PCI0.PRES.CSEL = Arg0
\_SB.PCI0.PRES.CEJ0 = One
Release (\_SB.PCI0.PRES.CPLK)
}
Method (CSCN, 0, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
{
Local4 = Zero
Local0 = One
Local1 = Zero
- While (((Local0 == One) && (Local3 < 0x0113)))
+ While (((Local0 == One) && (Local3 < 0x0104)))
{
Local0 = Zero
\_SB.PCI0.PRES.CSEL = Local3
\_SB.PCI0.PRES.CCMD = Zero
If ((\_SB.PCI0.PRES.CDAT < Local3))
{
Break
}
If ((Local1 == 0xFF))
{
Local4 = One
Break
}
Local3 = \_SB.PCI0.PRES.CDAT
@@ -7220,3281 +7145,3281 @@
Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
{
0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x81)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x81, Arg0, Arg1, Arg2)
}
}
- Processor (C082, 0x82, 0x00000000, 0x00)
+ Device (C082)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x82) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x82))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x82)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x82, Arg0, Arg1, Arg2)
}
}
- Processor (C083, 0x83, 0x00000000, 0x00)
+ Device (C083)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x83) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x83))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x83)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x83, Arg0, Arg1, Arg2)
}
}
- Processor (C084, 0x84, 0x00000000, 0x00)
+ Device (C084)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x84) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x84))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x84)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x84, Arg0, Arg1, Arg2)
}
}
[snip]
- Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ Device (C0FE)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0xFE) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0xFE))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00, 0x00, // ....|...
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0xFE)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0xFE, Arg0, Arg1, Arg2)
}
}
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-11-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
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Zhao Liu
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6dc82e3222 |
tests: bios-tables-test: Extend smbios core count2 test to cover general topology
The commit
|
|
|
Zhao Liu
|
c63fcb2c10 |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be changed about the type 4 core count2 test case. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-9-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Zhao Liu
|
61ace1d772 |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 3C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
[snip]
+ If ((Arg0 == 0x35))
+ {
+ Notify (C035, Arg1)
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-8-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
|
|
Zhao Liu
|
148a8a1d5f |
tests: bios-tables-test: Add test for smbios type4 core count
This tests the commit
|
|
|
Zhao Liu
|
623d26ad9a |
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 core count field. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-6-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
|
|
Zhao Liu
|
c1cd1d360d |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000430
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : C5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
+[3E5h 0997 1] Length : 08
+[3E6h 0998 1] Processor ID : 77
+[3E7h 0999 1] Local Apic ID : 9E
+[3E8h 1000 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
+[3EDh 1005 1] Length : 0C
+[3EEh 1006 1] I/O Apic ID : 00
+[3EFh 1007 1] Reserved : 00
+[3F0h 1008 4] Address : FEC00000
+[3F4h 1012 4] Interrupt : 00000000
+
+[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
+[3F9h 1017 1] Length : 0A
+[3FAh 1018 1] Bus : 00
+[3FBh 1019 1] Source : 00
+[3FCh 1020 4] Interrupt : 00000002
+[400h 1024 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
+[403h 1027 1] Length : 0A
+[404h 1028 1] Bus : 00
+[405h 1029 1] Source : 05
+[406h 1030 4] Interrupt : 00000005
+[40Ah 1034 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
+[40Dh 1037 1] Length : 0A
+[40Eh 1038 1] Bus : 00
+[40Fh 1039 1] Source : 09
+[410h 1040 4] Interrupt : 00000009
+[414h 1044 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
+[417h 1047 1] Length : 0A
+[418h 1048 1] Bus : 00
+[419h 1049 1] Source : 0A
+[41Ah 1050 4] Interrupt : 0000000A
+[41Eh 1054 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
+[421h 1057 1] Length : 0A
+[422h 1058 1] Bus : 00
+[423h 1059 1] Source : 0B
+[424h 1060 4] Interrupt : 0000000B
+[428h 1064 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
+[42Bh 1067 1] Length : 06
+[42Ch 1068 1] Processor ID : FF
+[42Dh 1069 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[42Fh 1071 1] Interrupt Input LINT : 01
+
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000489D (18589)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDB
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
[snip]
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C077, 0x77, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x77))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w.....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x77)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x77, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-5-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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