mirror of https://github.com/xemu-project/xemu.git
DVMA translation errors raise a module error irq (NMI)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3880 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
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4254fab8f9
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ff403da6a7
23
hw/iommu.c
23
hw/iommu.c
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@ -112,21 +112,28 @@ typedef struct IOMMUState {
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uint32_t regs[IOMMU_NREGS];
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uint32_t regs[IOMMU_NREGS];
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target_phys_addr_t iostart;
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target_phys_addr_t iostart;
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uint32_t version;
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uint32_t version;
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qemu_irq irq;
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} IOMMUState;
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} IOMMUState;
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static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
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static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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{
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IOMMUState *s = opaque;
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IOMMUState *s = opaque;
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target_phys_addr_t saddr;
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target_phys_addr_t saddr;
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uint32_t ret;
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saddr = (addr - s->addr) >> 2;
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saddr = (addr - s->addr) >> 2;
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switch (saddr) {
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switch (saddr) {
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default:
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default:
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DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
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ret = s->regs[saddr];
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return s->regs[saddr];
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break;
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case IOMMU_AFAR:
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case IOMMU_AFSR:
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ret = s->regs[saddr];
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qemu_irq_lower(s->irq);
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break;
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break;
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}
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}
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return 0;
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DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
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return ret;
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}
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}
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static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
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static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
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@ -180,8 +187,13 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
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DPRINTF("page flush %x\n", val);
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DPRINTF("page flush %x\n", val);
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s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
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s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
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break;
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break;
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case IOMMU_AFAR:
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s->regs[saddr] = val;
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qemu_irq_lower(s->irq);
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break;
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case IOMMU_AFSR:
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case IOMMU_AFSR:
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s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
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s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
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qemu_irq_lower(s->irq);
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break;
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break;
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case IOMMU_SBCFG0:
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case IOMMU_SBCFG0:
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case IOMMU_SBCFG1:
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case IOMMU_SBCFG1:
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@ -255,6 +267,7 @@ static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
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if (!is_write)
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if (!is_write)
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s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
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s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
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s->regs[IOMMU_AFAR] = addr;
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s->regs[IOMMU_AFAR] = addr;
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qemu_irq_raise(s->irq);
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}
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}
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
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@ -324,9 +337,10 @@ static void iommu_reset(void *opaque)
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s->regs[IOMMU_CTRL] = s->version;
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s->regs[IOMMU_CTRL] = s->version;
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s->regs[IOMMU_ARBEN] = IOMMU_MID;
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s->regs[IOMMU_ARBEN] = IOMMU_MID;
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s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
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s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
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qemu_irq_lower(s->irq);
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}
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}
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void *iommu_init(target_phys_addr_t addr, uint32_t version)
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void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
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{
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{
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IOMMUState *s;
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IOMMUState *s;
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int iommu_io_memory;
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int iommu_io_memory;
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@ -337,6 +351,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version)
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s->addr = addr;
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s->addr = addr;
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s->version = version;
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s->version = version;
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s->irq = irq;
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iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
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iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
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iommu_mem_write, s);
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iommu_mem_write, s);
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11
hw/sun4m.c
11
hw/sun4m.c
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@ -436,7 +436,6 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
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prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
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prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
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/* set up devices */
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/* set up devices */
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
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slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
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slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
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hwdef->intctl_base + 0x10000ULL,
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hwdef->intctl_base + 0x10000ULL,
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&hwdef->intbit_to_level[0],
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&hwdef->intbit_to_level[0],
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@ -451,6 +450,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
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prom_offset | IO_MEM_ROM);
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prom_offset | IO_MEM_ROM);
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}
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}
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
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slavio_irq[hwdef->me_irq]);
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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iommu, &espdma_irq, &esp_reset);
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iommu, &espdma_irq, &esp_reset);
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@ -597,7 +599,8 @@ static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
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slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
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slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
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&slavio_irq, cpu_irqs);
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&slavio_irq, cpu_irqs);
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
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slavio_irq[hwdef->me_irq]);
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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iommu, &espdma_irq, &esp_reset);
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iommu, &espdma_irq, &esp_reset);
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@ -1091,7 +1094,9 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
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for (i = 0; i < MAX_IOUNITS; i++)
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for (i = 0; i < MAX_IOUNITS; i++)
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if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
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if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
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iounits[i] = iommu_init(hwdef->iounit_bases[i], hwdef->iounit_version);
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iounits[i] = iommu_init(hwdef->iounit_bases[i],
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hwdef->iounit_version,
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sbi_irq[hwdef->me_irq]);
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espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
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espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
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iounits[0], &espdma_irq, &esp_reset);
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iounits[0], &espdma_irq, &esp_reset);
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@ -4,7 +4,7 @@
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/* Devices used by sparc32 system. */
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/* Devices used by sparc32 system. */
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/* iommu.c */
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/* iommu.c */
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void *iommu_init(target_phys_addr_t addr, uint32_t version);
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void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq);
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int is_write);
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uint8_t *buf, int len, int is_write);
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static inline void sparc_iommu_memory_read(void *opaque,
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static inline void sparc_iommu_memory_read(void *opaque,
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