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target/mips: Introduce mxu_translate_init() helper 

Extract the MXU register initialization code from mips_tcg_init()
as a new mxu_translate_init() helper. Make it public and replace
!TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to
elide this code at preprocessing time.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-13-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-17 21:21:17 +01:00
parent c7abe00ae9
commit fe35ea9483
2 changed files with 17 additions and 12 deletions
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28
target/mips/translate.c
View File

@ -2045,7 +2045,20 @@ static const char * const mxuregnames[] = {
"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
}; };
#endif
void mxu_translate_init(void)
{
for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
mxu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
mxuregnames[i]);
}
mxu_CR = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
}
#endif /* !TARGET_MIPS64 */
/* General purpose registers moves. */ /* General purpose registers moves. */
void gen_load_gpr(TCGv t, int reg) void gen_load_gpr(TCGv t, int reg)
@ -28047,18 +28060,9 @@ void mips_tcg_init(void)
cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval), cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
"llval"); "llval");
#if !defined(TARGET_MIPS64) if (TARGET_LONG_BITS == 32) {
for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_translate_init();
mxu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState,
active_tc.mxu_gpr[i]),
mxuregnames[i]);
} }
mxu_CR = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
#endif /* !TARGET_MIPS64 */
} }
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,

1
target/mips/translate.h
View File

@ -179,6 +179,7 @@ extern TCGv bcond;
void msa_translate_init(void); void msa_translate_init(void);
/* MXU */ /* MXU */
void mxu_translate_init(void);
bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
/* decodetree generated */ /* decodetree generated */