From fded775222f337d0fd2483d4cd1a89392204a6ee Mon Sep 17 00:00:00 2001 From: Matt Borgerson Date: Thu, 19 Jun 2025 01:55:06 -0700 Subject: [PATCH] nvnet: Clean up idle bit management --- hw/xbox/mcpx/nvnet/nvnet.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/hw/xbox/mcpx/nvnet/nvnet.c b/hw/xbox/mcpx/nvnet/nvnet.c index c18506aae4..2fc4303b41 100644 --- a/hw/xbox/mcpx/nvnet/nvnet.c +++ b/hw/xbox/mcpx/nvnet/nvnet.c @@ -225,10 +225,8 @@ static ssize_t nvnet_dma_packet_to_guest(NvNetState *s, const uint8_t *buf, PCIDevice *d = PCI_DEVICE(s); bool did_receive = false; - nvnet_set_reg(s, NVNET_TX_RX_CONTROL, - nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) & - ~NVNET_TX_RX_CONTROL_IDLE, - 4); + uint32_t ctrl = nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4); + nvnet_set_reg(s, NVNET_TX_RX_CONTROL, ctrl & ~NVNET_TX_RX_CONTROL_IDLE, 4); for (int i = 0; i < s->rx_ring_size; i++) { struct RingDesc desc; @@ -272,9 +270,8 @@ static ssize_t nvnet_dma_packet_to_guest(NvNetState *s, const uint8_t *buf, break; } - nvnet_set_reg( - s, NVNET_TX_RX_CONTROL, - nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) | NVNET_TX_RX_CONTROL_IDLE, 4); + ctrl = nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4); + nvnet_set_reg(s, NVNET_TX_RX_CONTROL, ctrl | NVNET_TX_RX_CONTROL_IDLE, 4); if (did_receive) { return size; @@ -289,10 +286,8 @@ static ssize_t nvnet_dma_packet_from_guest(NvNetState *s) PCIDevice *d = PCI_DEVICE(s); bool packet_sent = false; - nvnet_set_reg(s, NVNET_TX_RX_CONTROL, - nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) & - ~NVNET_TX_RX_CONTROL_IDLE, - 4); + uint32_t ctrl = nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4); + nvnet_set_reg(s, NVNET_TX_RX_CONTROL, ctrl & ~NVNET_TX_RX_CONTROL_IDLE, 4); for (int i = 0; i < s->tx_ring_size; i++) { struct RingDesc desc; @@ -346,9 +341,8 @@ static ssize_t nvnet_dma_packet_from_guest(NvNetState *s) nvnet_update_irq(s); } - nvnet_set_reg( - s, NVNET_TX_RX_CONTROL, - nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4) | NVNET_TX_RX_CONTROL_IDLE, 4); + ctrl = nvnet_get_reg(s, NVNET_TX_RX_CONTROL, 4); + nvnet_set_reg(s, NVNET_TX_RX_CONTROL, ctrl | NVNET_TX_RX_CONTROL_IDLE, 4); return 0; }