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target/s390x: Finish implementing RISBGN 

We added the entry to insn-data.def, but failed to update op_risbg
to match.  No need to special-case the imask inversion, since that
is already ~0 for RISBG (and now RISBGN).

Fixes: 375ee58bed
Fixes: https://bugs.launchpad.net/qemu/+bug/1701798 (s390x part)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20171107145546.767-1-richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
Richard Henderson 2017-11-07 15:55:46 +01:00 committed by Cornelia Huck
parent 2c28c49057
commit fdaae35143
1 changed files with 3 additions and 6 deletions
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9
target/s390x/translate.c
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@ -3432,6 +3432,7 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
/* Adjust the arguments for the specific insn. */ /* Adjust the arguments for the specific insn. */
switch (s->fields->op2) { switch (s->fields->op2) {
case 0x55: /* risbg */ case 0x55: /* risbg */
case 0x59: /* risbgn */
i3 &= 63; i3 &= 63;
i4 &= 63; i4 &= 63;
pmask = ~0; pmask = ~0;
@ -3447,7 +3448,7 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
pmask = 0x00000000ffffffffull; pmask = 0x00000000ffffffffull;
break; break;
default: default:
abort(); g_assert_not_reached();
} }
/* MASK is the set of bits to be inserted from R2. /* MASK is the set of bits to be inserted from R2.
@ -3464,11 +3465,7 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
insns, we need to keep the other half of the register. */ insns, we need to keep the other half of the register. */
imask = ~mask | ~pmask; imask = ~mask | ~pmask;
if (do_zero) { if (do_zero) {
if (s->fields->op2 == 0x55) { imask = ~pmask;
imask = 0;
} else {
imask = ~pmask;
}
} }
len = i4 - i3 + 1; len = i4 - i3 + 1;