diff --git a/configs/devices/or1k-softmmu/default.mak b/configs/devices/or1k-softmmu/default.mak
index 168101c39a..89c39e3123 100644
--- a/configs/devices/or1k-softmmu/default.mak
+++ b/configs/devices/or1k-softmmu/default.mak
@@ -3,3 +3,4 @@
# Boards:
#
CONFIG_OR1K_SIM=y
+CONFIG_OR1K_VIRT=y
diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak
index 263e970870..432f855a30 100644
--- a/configs/targets/or1k-softmmu.mak
+++ b/configs/targets/or1k-softmmu.mak
@@ -1,3 +1,4 @@
TARGET_ARCH=openrisc
+TARGET_SUPPORTS_MTTCG=y
TARGET_BIG_ENDIAN=y
TARGET_NEED_FDT=y
diff --git a/docs/system/openrisc/cpu-features.rst b/docs/system/openrisc/cpu-features.rst
new file mode 100644
index 0000000000..aeb65e22ff
--- /dev/null
+++ b/docs/system/openrisc/cpu-features.rst
@@ -0,0 +1,15 @@
+CPU Features
+============
+
+The QEMU emulation of the OpenRISC architecture provides following built in
+features.
+
+- Shadow GPRs
+- MMU TLB with 128 entries, 1 way
+- Power Management (PM)
+- Programmable Interrupt Controller (PIC)
+- Tick Timer
+
+These features are on by default and the presence can be confirmed by checking
+the contents of the Unit Presence Register (``UPR``) and CPU Configuration
+Register (``CPUCFGR``).
diff --git a/docs/system/openrisc/emulation.rst b/docs/system/openrisc/emulation.rst
new file mode 100644
index 0000000000..0af898ab20
--- /dev/null
+++ b/docs/system/openrisc/emulation.rst
@@ -0,0 +1,17 @@
+OpenRISC 1000 CPU architecture support
+======================================
+
+QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of
+the OpenRISC 1000 cpu architecture.
+
+The or1200 cpu also has support for the following instruction subsets:
+
+- ORBIS32 (OpenRISC Basic Instruction Set)
+- ORFPX32 (OpenRISC Floating-Point eXtension)
+
+In addition to the instruction subsets the QEMU TCG emulation also has support
+for most Class II (optional) instructions.
+
+For information on all OpenRISC instructions please refer to the latest
+architecture manual available on the OpenRISC website in the
+`OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
diff --git a/docs/system/openrisc/or1k-sim.rst b/docs/system/openrisc/or1k-sim.rst
new file mode 100644
index 0000000000..ef10439737
--- /dev/null
+++ b/docs/system/openrisc/or1k-sim.rst
@@ -0,0 +1,43 @@
+Or1ksim board
+=============
+
+The QEMU Or1ksim machine emulates the standard OpenRISC board simulator which is
+also the standard SoC configuration.
+
+Supported devices
+-----------------
+
+ * 16550A UART
+ * ETHOC Ethernet controller
+ * SMP (OpenRISC multicore using ompic)
+
+Boot options
+------------
+
+The Or1ksim machine can be started using the ``-kernel`` and ``-initrd`` options
+to load a Linux kernel and optional disk image.
+
+.. code-block:: bash
+
+ $ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
+ -kernel vmlinux \
+ -initrd initramfs.cpio.gz \
+ -m 128
+
+Linux guest kernel configuration
+""""""""""""""""""""""""""""""""
+
+The 'or1ksim_defconfig' for Linux openrisc kernels includes the right
+drivers for the or1ksim machine. If you would like to run an SMP system
+choose the 'simple_smp_defconfig' config.
+
+Hardware configuration information
+""""""""""""""""""""""""""""""""""
+
+The ``or1k-sim`` board automatically generates a device tree blob ("dtb")
+which it passes to the guest. This provides information about the
+addresses, interrupt lines and other configuration of the various devices
+in the system.
+
+The location of the DTB will be passed in register ``r3`` to the guest operating
+system.
diff --git a/docs/system/openrisc/virt.rst b/docs/system/openrisc/virt.rst
new file mode 100644
index 0000000000..2fe61ac942
--- /dev/null
+++ b/docs/system/openrisc/virt.rst
@@ -0,0 +1,50 @@
+'virt' generic virtual platform
+===============================
+
+The ``virt`` board is a platform which does not correspond to any
+real hardware; it is designed for use in virtual machines.
+It is the recommended board type if you simply want to run
+a guest such as Linux and do not care about reproducing the
+idiosyncrasies and limitations of a particular bit of real-world
+hardware.
+
+Supported devices
+-----------------
+
+ * PCI/PCIe devices
+ * 8 virtio-mmio transport devices
+ * 16550A UART
+ * Goldfish RTC
+ * SiFive Test device for poweroff and reboot
+ * SMP (OpenRISC multicore using ompic)
+
+Boot options
+------------
+
+The virt machine can be started using the ``-kernel`` and ``-initrd`` options
+to load a Linux kernel and optional disk image. For example:
+
+.. code-block:: bash
+
+ $ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
+ -device virtio-net-device,netdev=user -netdev user,id=user,net=10.9.0.1/24,host=10.9.0.100 \
+ -device virtio-blk-device,drive=d0 -drive file=virt.qcow2,id=d0,if=none,format=qcow2 \
+ -kernel vmlinux \
+ -initrd initramfs.cpio.gz \
+ -m 128
+
+Linux guest kernel configuration
+""""""""""""""""""""""""""""""""
+
+The 'virt_defconfig' for Linux openrisc kernels includes the right drivers for
+the ``virt`` machine.
+
+Hardware configuration information
+""""""""""""""""""""""""""""""""""
+
+The ``virt`` board automatically generates a device tree blob ("dtb") which it
+passes to the guest. This provides information about the addresses, interrupt
+lines and other configuration of the various devices in the system.
+
+The location of the DTB will be passed in register ``r3`` to the guest operating
+system.
diff --git a/docs/system/target-openrisc.rst b/docs/system/target-openrisc.rst
new file mode 100644
index 0000000000..22cb2217a6
--- /dev/null
+++ b/docs/system/target-openrisc.rst
@@ -0,0 +1,71 @@
+.. _OpenRISC-System-emulator:
+
+OpenRISC System emulator
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+QEMU can emulate 32-bit OpenRISC CPUs using the ``qemu-system-or1k`` executable.
+
+OpenRISC CPUs are generally built into "system-on-chip" (SoC) designs that run
+on FPGAs. These SoCs are based on the same core architecture as the or1ksim
+(the original OpenRISC instruction level simulator) which QEMU supports. For
+this reason QEMU does not need to support many different boards to support the
+OpenRISC hardware ecosystem.
+
+The OpenRISC CPU supported by QEMU is the ``or1200``, it supports an MMU and can
+run linux.
+
+Choosing a board model
+======================
+
+For QEMU's OpenRISC system emulation, you must specify which board model you
+want to use with the ``-M`` or ``--machine`` option; the default machine is
+``or1k-sim``.
+
+If you intend to boot Linux, it is possible to have a single kernel image that
+will boot on any of the QEMU machines. To do this one would compile all required
+drivers into the kernel. This is possible because QEMU will create a device tree
+structure that describes the QEMU machine and pass a pointer to the structure to
+the kernel. The kernel can then use this to configure itself for the machine.
+
+However, typically users will have specific firmware images for a specific machine.
+
+If you already have a system image or a kernel that works on hardware and you
+want to boot with QEMU, check whether QEMU lists that machine in its ``-machine
+help`` output. If it is listed, then you can probably use that board model. If
+it is not listed, then unfortunately your image will almost certainly not boot
+on QEMU. (You might be able to extract the filesystem and use that with a
+different kernel which boots on a system that QEMU does emulate.)
+
+If you don't care about reproducing the idiosyncrasies of a particular
+bit of hardware, such as small amount of RAM, no PCI or other hard disk, etc.,
+and just want to run Linux, the best option is to use the ``virt`` board. This
+is a platform which doesn't correspond to any real hardware and is designed for
+use in virtual machines. You'll need to compile Linux with a suitable
+configuration for running on the ``virt`` board. ``virt`` supports PCI, virtio
+and large amounts of RAM.
+
+Board-specific documentation
+============================
+
+..
+ This table of contents should be kept sorted alphabetically
+ by the title text of each file, which isn't the same ordering
+ as an alphabetical sort by filename.
+
+.. toctree::
+ :maxdepth: 1
+
+ openrisc/or1k-sim
+ openrisc/virt
+
+Emulated CPU architecture support
+=================================
+
+.. toctree::
+ openrisc/emulation
+
+OpenRISC CPU features
+=====================
+
+.. toctree::
+ openrisc/cpu-features
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 9dcd95dd84..224fadae71 100644
--- a/docs/system/targets.rst
+++ b/docs/system/targets.rst
@@ -21,6 +21,7 @@ Contents:
target-m68k
target-mips
target-ppc
+ target-openrisc
target-riscv
target-rx
target-s390x
diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c
index 3122c8ef2c..2f3ffc0de6 100644
--- a/hw/m68k/virt.c
+++ b/hw/m68k/virt.c
@@ -173,6 +173,7 @@ static void virt_init(MachineState *machine)
io_base = VIRT_GF_RTC_MMIO_BASE;
for (i = 0; i < VIRT_GF_RTC_NB; i++) {
dev = qdev_new(TYPE_GOLDFISH_RTC);
+ qdev_prop_set_bit(dev, "big-endian", true);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, io_base);
diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig
index 8f284f3ba0..97af258b55 100644
--- a/hw/openrisc/Kconfig
+++ b/hw/openrisc/Kconfig
@@ -4,3 +4,15 @@ config OR1K_SIM
select OPENCORES_ETH
select OMPIC
select SPLIT_IRQ
+
+config OR1K_VIRT
+ bool
+ imply PCI_DEVICES
+ imply VIRTIO_VGA
+ imply TEST_DEVICES
+ select PCI
+ select PCI_EXPRESS_GENERIC_BRIDGE
+ select GOLDFISH_RTC
+ select SERIAL
+ select SIFIVE_TEST
+ select VIRTIO_MMIO
diff --git a/hw/openrisc/boot.c b/hw/openrisc/boot.c
new file mode 100644
index 0000000000..128ccbcba2
--- /dev/null
+++ b/hw/openrisc/boot.c
@@ -0,0 +1,116 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * QEMU OpenRISC boot helpers.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/cpu-defs.h"
+#include "elf.h"
+#include "hw/loader.h"
+#include "hw/openrisc/boot.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/qtest.h"
+
+#include <libfdt.h>
+
+#define KERNEL_LOAD_ADDR 0x100
+
+hwaddr openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ uint32_t *bootstrap_pc)
+{
+ long kernel_size;
+ uint64_t elf_entry;
+ uint64_t high_addr;
+ hwaddr entry;
+
+ if (kernel_filename && !qtest_enabled()) {
+ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
+ &elf_entry, NULL, &high_addr, NULL, 1,
+ EM_OPENRISC, 1, 0);
+ entry = elf_entry;
+ if (kernel_size < 0) {
+ kernel_size = load_uimage(kernel_filename,
+ &entry, NULL, NULL, NULL, NULL);
+ high_addr = entry + kernel_size;
+ }
+ if (kernel_size < 0) {
+ kernel_size = load_image_targphys(kernel_filename,
+ KERNEL_LOAD_ADDR,
+ ram_size - KERNEL_LOAD_ADDR);
+ high_addr = KERNEL_LOAD_ADDR + kernel_size;
+ }
+
+ if (entry <= 0) {
+ entry = KERNEL_LOAD_ADDR;
+ }
+
+ if (kernel_size < 0) {
+ error_report("couldn't load the kernel '%s'", kernel_filename);
+ exit(1);
+ }
+ *bootstrap_pc = entry;
+
+ return high_addr;
+ }
+ return 0;
+}
+
+hwaddr openrisc_load_initrd(void *fdt, const char *filename,
+ hwaddr load_start, uint64_t mem_size)
+{
+ int size;
+ hwaddr start;
+
+ /* We put the initrd right after the kernel; page aligned. */
+ start = TARGET_PAGE_ALIGN(load_start);
+
+ size = load_ramdisk(filename, start, mem_size - start);
+ if (size < 0) {
+ size = load_image_targphys(filename, start, mem_size - start);
+ if (size < 0) {
+ error_report("could not load ramdisk '%s'", filename);
+ exit(1);
+ }
+ }
+
+ if (fdt) {
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-end", start + size);
+ }
+
+ return start + size;
+}
+
+uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
+ uint64_t mem_size)
+{
+ uint32_t fdt_addr;
+ int ret;
+ int fdtsize = fdt_totalsize(fdt);
+
+ if (fdtsize <= 0) {
+ error_report("invalid device-tree");
+ exit(1);
+ }
+
+ /* We put fdt right after the kernel and/or initrd. */
+ fdt_addr = TARGET_PAGE_ALIGN(load_start);
+
+ ret = fdt_pack(fdt);
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
+ /* copy in the device tree */
+ qemu_fdt_dumpdtb(fdt, fdtsize);
+
+ rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
+ &address_space_memory);
+
+ return fdt_addr;
+}
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 93268815d8..10163b391b 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "migration/vmstate.h"
#include "qemu/timer.h"
+#include "sysemu/reset.h"
#define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */
@@ -122,6 +123,24 @@ static void openrisc_timer_cb(void *opaque)
qemu_cpu_kick(CPU(cpu));
}
+/* Reset the per CPU counter state. */
+static void openrisc_count_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+
+ if (cpu->env.is_counting) {
+ cpu_openrisc_count_stop(cpu);
+ }
+ cpu->env.ttmr = 0x00000000;
+}
+
+/* Reset the global timer state. */
+static void openrisc_timer_reset(void *opaque)
+{
+ or1k_timer->ttcr = 0x00000000;
+ or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+}
+
static const VMStateDescription vmstate_or1k_timer = {
.name = "or1k_timer",
.version_id = 1,
@@ -136,10 +155,11 @@ static const VMStateDescription vmstate_or1k_timer = {
void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
{
cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);
- cpu->env.ttmr = 0x00000000;
+ qemu_register_reset(openrisc_count_reset, cpu);
if (or1k_timer == NULL) {
or1k_timer = g_new0(OR1KTimerState, 1);
+ qemu_register_reset(openrisc_timer_reset, cpu);
vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
}
}
diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build
index ec48172c9d..2dbc6365bb 100644
--- a/hw/openrisc/meson.build
+++ b/hw/openrisc/meson.build
@@ -1,5 +1,7 @@
openrisc_ss = ss.source_set()
openrisc_ss.add(files('cputimer.c'))
+openrisc_ss.add(files('boot.c'))
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: [files('openrisc_sim.c'), fdt])
+openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: [files('virt.c'), fdt])
hw_arch += {'openrisc': openrisc_ss}
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 35adce17ac..35da123aef 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -24,10 +24,9 @@
#include "cpu.h"
#include "hw/irq.h"
#include "hw/boards.h"
-#include "elf.h"
#include "hw/char/serial.h"
#include "net/net.h"
-#include "hw/loader.h"
+#include "hw/openrisc/boot.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
#include "sysemu/device_tree.h"
@@ -283,101 +282,6 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
g_free(nodename);
}
-static hwaddr openrisc_load_kernel(ram_addr_t ram_size,
- const char *kernel_filename)
-{
- long kernel_size;
- uint64_t elf_entry;
- uint64_t high_addr;
- hwaddr entry;
-
- if (kernel_filename && !qtest_enabled()) {
- kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
- &elf_entry, NULL, &high_addr, NULL, 1,
- EM_OPENRISC, 1, 0);
- entry = elf_entry;
- if (kernel_size < 0) {
- kernel_size = load_uimage(kernel_filename,
- &entry, NULL, NULL, NULL, NULL);
- high_addr = entry + kernel_size;
- }
- if (kernel_size < 0) {
- kernel_size = load_image_targphys(kernel_filename,
- KERNEL_LOAD_ADDR,
- ram_size - KERNEL_LOAD_ADDR);
- high_addr = KERNEL_LOAD_ADDR + kernel_size;
- }
-
- if (entry <= 0) {
- entry = KERNEL_LOAD_ADDR;
- }
-
- if (kernel_size < 0) {
- error_report("couldn't load the kernel '%s'", kernel_filename);
- exit(1);
- }
- boot_info.bootstrap_pc = entry;
-
- return high_addr;
- }
- return 0;
-}
-
-static hwaddr openrisc_load_initrd(Or1ksimState *state, const char *filename,
- hwaddr load_start, uint64_t mem_size)
-{
- void *fdt = state->fdt;
- int size;
- hwaddr start;
-
- /* We put the initrd right after the kernel; page aligned. */
- start = TARGET_PAGE_ALIGN(load_start);
-
- size = load_ramdisk(filename, start, mem_size - start);
- if (size < 0) {
- size = load_image_targphys(filename, start, mem_size - start);
- if (size < 0) {
- error_report("could not load ramdisk '%s'", filename);
- exit(1);
- }
- }
-
- qemu_fdt_setprop_cell(fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(fdt, "/chosen",
- "linux,initrd-end", start + size);
-
- return start + size;
-}
-
-static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start,
- uint64_t mem_size)
-{
- void *fdt = state->fdt;
- uint32_t fdt_addr;
- int ret;
- int fdtsize = fdt_totalsize(fdt);
-
- if (fdtsize <= 0) {
- error_report("invalid device-tree");
- exit(1);
- }
-
- /* We put fdt right after the kernel and/or initrd. */
- fdt_addr = TARGET_PAGE_ALIGN(load_start);
-
- ret = fdt_pack(fdt);
- /* Should only fail if we've built a corrupted tree */
- g_assert(ret == 0);
- /* copy in the device tree */
- qemu_fdt_dumpdtb(fdt, fdtsize);
-
- rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
- &address_space_memory);
-
- return fdt_addr;
-}
-
static void openrisc_sim_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
@@ -428,13 +332,15 @@ static void openrisc_sim_init(MachineState *machine)
or1ksim_memmap[OR1KSIM_UART].size,
smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
- load_addr = openrisc_load_kernel(ram_size, kernel_filename);
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
if (load_addr > 0) {
if (machine->initrd_filename) {
- load_addr = openrisc_load_initrd(state, machine->initrd_filename,
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
load_addr, machine->ram_size);
}
- boot_info.fdt_addr = openrisc_load_fdt(state, load_addr,
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
machine->ram_size);
}
}
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
new file mode 100644
index 0000000000..f8a68a6a6b
--- /dev/null
+++ b/hw/openrisc/virt.c
@@ -0,0 +1,571 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * OpenRISC QEMU virtual machine.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "exec/address-spaces.h"
+#include "hw/irq.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/core/split-irq.h"
+#include "hw/openrisc/boot.h"
+#include "hw/misc/sifive_test.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/qdev-properties.h"
+#include "hw/rtc/goldfish_rtc.h"
+#include "hw/sysbus.h"
+#include "hw/virtio/virtio-mmio.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+
+#include <libfdt.h>
+
+#define VIRT_CPUS_MAX 4
+#define VIRT_CLK_MHZ 20000000
+
+#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
+#define VIRT_MACHINE(obj) \
+ OBJECT_CHECK(OR1KVirtState, (obj), TYPE_VIRT_MACHINE)
+
+typedef struct OR1KVirtState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ void *fdt;
+ int fdt_size;
+
+} OR1KVirtState;
+
+enum {
+ VIRT_DRAM,
+ VIRT_ECAM,
+ VIRT_MMIO,
+ VIRT_PIO,
+ VIRT_TEST,
+ VIRT_RTC,
+ VIRT_VIRTIO,
+ VIRT_UART,
+ VIRT_OMPIC,
+};
+
+enum {
+ VIRT_OMPIC_IRQ = 1,
+ VIRT_UART_IRQ = 2,
+ VIRT_RTC_IRQ = 3,
+ VIRT_VIRTIO_IRQ = 4, /* to 12 */
+ VIRTIO_COUNT = 8,
+ VIRT_PCI_IRQ_BASE = 13, /* to 17 */
+};
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} virt_memmap[] = {
+ [VIRT_DRAM] = { 0x00000000, 0 },
+ [VIRT_UART] = { 0x90000000, 0x100 },
+ [VIRT_TEST] = { 0x96000000, 0x8 },
+ [VIRT_RTC] = { 0x96005000, 0x1000 },
+ [VIRT_VIRTIO] = { 0x97000000, 0x1000 },
+ [VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 },
+ [VIRT_ECAM] = { 0x9e000000, 0x1000000 },
+ [VIRT_PIO] = { 0x9f000000, 0x1000000 },
+ [VIRT_MMIO] = { 0xa0000000, 0x10000000 },
+};
+
+static struct openrisc_boot_info {
+ uint32_t bootstrap_pc;
+ uint32_t fdt_addr;
+} boot_info;
+
+static void main_cpu_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ cpu_reset(CPU(cpu));
+
+ cpu_set_pc(cs, boot_info.bootstrap_pc);
+ cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
+}
+
+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
+{
+ return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
+}
+
+static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
+{
+ int i;
+
+ if (num_cpus > 1) {
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ return qdev_get_gpio_in(splitter, 0);
+ } else {
+ return get_cpu_irq(cpus, 0, irq_pin);
+ }
+}
+
+static void openrisc_create_fdt(OR1KVirtState *state,
+ const struct MemmapEntry *memmap,
+ int num_cpus, uint64_t mem_size,
+ const char *cmdline,
+ int32_t *pic_phandle)
+{
+ void *fdt;
+ int cpu;
+ char *nodename;
+ uint8_t rng_seed[32];
+
+ fdt = state->fdt = create_device_tree(&state->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
+
+ qemu_fdt_add_subnode(fdt, "/soc");
+ qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
+
+ nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
+ memmap[VIRT_DRAM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ memmap[VIRT_DRAM].base, mem_size);
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
+ g_free(nodename);
+
+ qemu_fdt_add_subnode(fdt, "/cpus");
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+
+ for (cpu = 0; cpu < num_cpus; cpu++) {
+ nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1200-rtlsvn481");
+ qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ VIRT_CLK_MHZ);
+ g_free(nodename);
+ }
+
+ nodename = (char *)"/pic";
+ qemu_fdt_add_subnode(fdt, nodename);
+ *pic_phandle = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1k-pic-level");
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle);
+
+ qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", *pic_phandle);
+
+ qemu_fdt_add_subnode(fdt, "/chosen");
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
+
+ /* Pass seed to RNG. */
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+
+ /* Create aliases node for use by devices. */
+ qemu_fdt_add_subnode(fdt, "/aliases");
+}
+
+static void openrisc_virt_ompic_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ DeviceState *dev;
+ SysBusDevice *s;
+ char *nodename;
+ int i;
+
+ dev = qdev_new("or1k-ompic");
+ qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ sysbus_mmio_map(s, 0, base);
+
+ /* Add device tree node for ompic. */
+ nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
+ serial_hd(0), DEVICE_NATIVE_ENDIAN);
+
+ /* Add device tree node for serial. */
+ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+
+ /* The /chosen node is created during fdt creation. */
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
+ qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ g_free(nodename);
+}
+
+static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size)
+{
+ void *fdt = state->fdt;
+ int test_ph;
+ char *nodename;
+
+ /* SiFive Test MMIO device */
+ sifive_test_create(base);
+
+ /* SiFive Test MMIO Reset device FDT */
+ nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon");
+ test_ph = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/reboot");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/poweroff");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
+ g_free(nodename);
+
+}
+
+static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ qemu_irq rtc_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* Goldfish RTC */
+ sysbus_create_simple(TYPE_GOLDFISH_RTC, base, rtc_irq);
+
+ /* Goldfish RTC FDT */
+ nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "google,goldfish-rtc");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+
+}
+
+static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
+ uint32_t irqchip_phandle)
+{
+ int pin, dev;
+ uint32_t irq_map_stride = 0;
+ uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {};
+ uint32_t *irq_map = full_irq_map;
+
+ /*
+ * This code creates a standard swizzle of interrupts such that
+ * each device's first interrupt is based on it's PCI_SLOT number.
+ * (See pci_swizzle_map_irq_fn())
+ *
+ * We only need one entry per interrupt in the table (not one per
+ * possible slot) seeing the interrupt-map-mask will allow the table
+ * to wrap to any number of devices.
+ */
+ for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
+ int devfn = dev << 3;
+
+ for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
+ int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+ int i = 0;
+
+ /* Fill PCI address cells */
+ irq_map[i++] = cpu_to_be32(devfn << 8);
+ irq_map[i++] = 0;
+ irq_map[i++] = 0;
+
+ /* Fill PCI Interrupt cells */
+ irq_map[i++] = cpu_to_be32(pin + 1);
+
+ /* Fill interrupt controller phandle and cells */
+ irq_map[i++] = cpu_to_be32(irqchip_phandle);
+ irq_map[i++] = cpu_to_be32(irq_nr);
+
+ if (!irq_map_stride) {
+ irq_map_stride = i;
+ }
+ irq_map += irq_map_stride;
+ }
+ }
+
+ qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
+ GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+ irq_map_stride * sizeof(uint32_t));
+
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+ 0x1800, 0, 0, 0x7);
+}
+
+static void openrisc_virt_pcie_init(OR1KVirtState *state,
+ hwaddr ecam_base, hwaddr ecam_size,
+ hwaddr pio_base, hwaddr pio_size,
+ hwaddr mmio_base, hwaddr mmio_size,
+ int num_cpus, OpenRISCCPU *cpus[],
+ int irq_base, int32_t pic_phandle)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ MemoryRegion *alias;
+ MemoryRegion *reg;
+ DeviceState *dev;
+ qemu_irq pcie_irq;
+ int i;
+
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ /* Map ECAM space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-ecam",
+ reg, 0, ecam_size);
+ memory_region_add_subregion(get_system_memory(), ecam_base, alias);
+
+ /*
+ * Map the MMIO window into system address space so as to expose
+ * the section of PCI MMIO space which starts at the same base address
+ * (ie 1:1 mapping for that part of PCI MMIO space visible through
+ * the window).
+ */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-mmio",
+ reg, mmio_base, mmio_size);
+ memory_region_add_subregion(get_system_memory(), mmio_base, alias);
+
+ /* Map IO port space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-pio",
+ reg, 0, pio_size);
+ memory_region_add_subregion(get_system_memory(), pio_base, alias);
+
+ /* Connect IRQ lines. */
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq);
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
+ }
+
+ nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3);
+ qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "pci-host-ecam-generic");
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+ qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
+ ecam_size / PCIE_MMCFG_SIZE_MIN - 1);
+ qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size);
+ /* pci-address(3) cpu-address(1) pci-size(2) */
+ qemu_fdt_setprop_cells(fdt, nodename, "ranges",
+ FDT_PCI_RANGE_IOPORT, 0, 0,
+ pio_base, 0, pio_size,
+ FDT_PCI_RANGE_MMIO, 0, mmio_base,
+ mmio_base, 0, mmio_size);
+
+ create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle);
+ g_free(nodename);
+}
+
+static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ DeviceState *dev;
+ SysBusDevice *sysbus;
+ qemu_irq virtio_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* VirtIO MMIO devices */
+ dev = qdev_new(TYPE_VIRTIO_MMIO);
+ qdev_prop_set_bit(dev, "force-legacy", false);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ sysbus_connect_irq(sysbus, 0, virtio_irq);
+ sysbus_mmio_map(sysbus, 0, base);
+
+ /* VirtIO MMIO devices FDT */
+ nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_init(MachineState *machine)
+{
+ ram_addr_t ram_size = machine->ram_size;
+ const char *kernel_filename = machine->kernel_filename;
+ OpenRISCCPU *cpus[VIRT_CPUS_MAX] = {};
+ OR1KVirtState *state = VIRT_MACHINE(machine);
+ MemoryRegion *ram;
+ hwaddr load_addr;
+ int n;
+ unsigned int smp_cpus = machine->smp.cpus;
+ int32_t pic_phandle;
+
+ assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
+ for (n = 0; n < smp_cpus; n++) {
+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
+ if (cpus[n] == NULL) {
+ fprintf(stderr, "Unable to find CPU definition!\n");
+ exit(1);
+ }
+
+ cpu_openrisc_clock_init(cpus[n]);
+
+ qemu_register_reset(main_cpu_reset, cpus[n]);
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
+ machine->kernel_cmdline, &pic_phandle);
+
+ if (smp_cpus > 1) {
+ openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
+ virt_memmap[VIRT_OMPIC].size,
+ smp_cpus, cpus, VIRT_OMPIC_IRQ);
+ }
+
+ openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base,
+ virt_memmap[VIRT_UART].size,
+ smp_cpus, cpus, VIRT_UART_IRQ);
+
+ openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base,
+ virt_memmap[VIRT_TEST].size);
+
+ openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base,
+ virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
+ VIRT_RTC_IRQ);
+
+ openrisc_virt_pcie_init(state, virt_memmap[VIRT_ECAM].base,
+ virt_memmap[VIRT_ECAM].size,
+ virt_memmap[VIRT_PIO].base,
+ virt_memmap[VIRT_PIO].size,
+ virt_memmap[VIRT_MMIO].base,
+ virt_memmap[VIRT_MMIO].size,
+ smp_cpus, cpus,
+ VIRT_PCI_IRQ_BASE, pic_phandle);
+
+ for (n = 0; n < VIRTIO_COUNT; n++) {
+ openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
+ + n * virt_memmap[VIRT_VIRTIO].size,
+ virt_memmap[VIRT_VIRTIO].size,
+ smp_cpus, cpus, VIRT_VIRTIO_IRQ + n);
+ }
+
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
+ if (load_addr > 0) {
+ if (machine->initrd_filename) {
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
+ load_addr, machine->ram_size);
+ }
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
+ machine->ram_size);
+ }
+}
+
+static void openrisc_virt_machine_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "or1k virtual machine";
+ mc->init = openrisc_virt_init;
+ mc->max_cpus = VIRT_CPUS_MAX;
+ mc->is_default = false;
+ mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
+}
+
+static const TypeInfo or1ksim_machine_typeinfo = {
+ .name = TYPE_VIRT_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = openrisc_virt_machine_init,
+ .instance_size = sizeof(OR1KVirtState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+ type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
index 35e493be31..19a56402a0 100644
--- a/hw/rtc/goldfish_rtc.c
+++ b/hw/rtc/goldfish_rtc.c
@@ -216,14 +216,25 @@ static int goldfish_rtc_post_load(void *opaque, int version_id)
return 0;
}
-static const MemoryRegionOps goldfish_rtc_ops = {
- .read = goldfish_rtc_read,
- .write = goldfish_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4
- }
+static const MemoryRegionOps goldfish_rtc_ops[2] = {
+ [false] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
+ [true] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
};
static const VMStateDescription goldfish_rtc_vmstate = {
@@ -265,7 +276,8 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
SysBusDevice *dev = SYS_BUS_DEVICE(d);
GoldfishRTCState *s = GOLDFISH_RTC(d);
- memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s),
+ &goldfish_rtc_ops[s->big_endian], s,
"goldfish_rtc", 0x24);
sysbus_init_mmio(dev, &s->iomem);
@@ -274,10 +286,17 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
}
+static Property goldfish_rtc_properties[] = {
+ DEFINE_PROP_BOOL("big-endian", GoldfishRTCState, big_endian,
+ false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void goldfish_rtc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ device_class_set_props(dc, goldfish_rtc_properties);
dc->realize = goldfish_rtc_realize;
dc->reset = goldfish_rtc_reset;
dc->vmsd = &goldfish_rtc_vmstate;
diff --git a/include/hw/openrisc/boot.h b/include/hw/openrisc/boot.h
new file mode 100644
index 0000000000..25a313d63a
--- /dev/null
+++ b/include/hw/openrisc/boot.h
@@ -0,0 +1,34 @@
+/*
+ * QEMU OpenRISC boot helpers.
+ *
+ * Copyright (c) 2022 Stafford Horne <shorne@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef OPENRISC_BOOT_H
+#define OPENRISC_BOOT_H
+
+#include "exec/cpu-defs.h"
+
+hwaddr openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ uint32_t *bootstrap_pc);
+
+hwaddr openrisc_load_initrd(void *fdt, const char *filename,
+ hwaddr load_start, uint64_t mem_size);
+
+uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
+ uint64_t mem_size);
+
+#endif /* OPENRISC_BOOT_H */
diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h
index 79ca7daf5d..162be33863 100644
--- a/include/hw/rtc/goldfish_rtc.h
+++ b/include/hw/rtc/goldfish_rtc.h
@@ -42,6 +42,8 @@ struct GoldfishRTCState {
uint32_t irq_pending;
uint32_t irq_enabled;
uint32_t time_high;
+
+ bool big_endian;
};
#endif
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -98,7 +98,6 @@ static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- cpu->env.picsr = 0;
}
}
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b9584f10d4..1d5efa5ca2 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -25,6 +25,8 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
+#define TCG_GUEST_DEFAULT_MO (0)
+
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index e5724f5371..c31c6f12c4 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
[EXCP_TRAP] = "TRAP",
};
- qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
+ qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
+ cs->cpu_index,
+ int_name[exception]);
hwaddr vect_pc = exception << 8;
if (env->cpucfgr & CPUCFGR_EVBARP) {
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case SR_DME | SR_IME:
/* The mmu is definitely enabled. */
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
- PAGE_EXEC | PAGE_READ | PAGE_WRITE,
+ PAGE_READ,
+ (sr & SR_SM) != 0);
+ if (!excp) {
+ return phys_addr;
+ }
+ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
+ PAGE_EXEC,
(sr & SR_SM) != 0);
return excp ? -1 : phys_addr;
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 48674231e7..09b3c97d7c 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -139,12 +139,20 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(9, 0): /* PICMR */
env->picmr = rb;
+ qemu_mutex_lock_iothread();
+ if (env->picsr & env->picmr) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ qemu_mutex_unlock_iothread();
break;
case TO_SPR(9, 2): /* PICSR */
env->picsr &= ~rb;
break;
case TO_SPR(10, 0): /* TTMR */
{
+ qemu_mutex_lock_iothread();
if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
switch (rb & TTMR_M) {
case TIMER_NONE:
@@ -168,14 +176,16 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
env->ttmr = rb & ~TTMR_IP;
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
-
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
}
break;
case TO_SPR(10, 1): /* TTCR */
+ qemu_mutex_lock_iothread();
cpu_openrisc_count_set(cpu, rb);
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
break;
#endif
@@ -303,7 +313,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
return env->ttmr;
case TO_SPR(10, 1): /* TTCR */
+ qemu_mutex_lock_iothread();
cpu_openrisc_count_update(cpu);
+ qemu_mutex_unlock_iothread();
return cpu_openrisc_count_get(cpu);
#endif