mirror of https://github.com/xemu-project/xemu.git
target/sh4: convert to TranslatorOps
This was fairly straightforward since it had already been converted to DisasContextBase; just had to add TARGET_TOO_MANY to the switch in tb_stop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Emilio G. Cota
Richard Henderson
parent
b542683d77
commit
fd1b3d3864
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@ -2258,126 +2258,127 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
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}
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#endif
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUSH4State *env = cs->env_ptr;
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DisasContext ctx;
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target_ulong pc_start;
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int num_insns;
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int max_insns;
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int bound;
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pc_start = tb->pc;
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ctx.base.pc_next = pc_start;
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ctx.tbflags = (uint32_t)tb->flags;
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ctx.envflags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
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ctx.base.is_jmp = DISAS_NEXT;
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ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
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ctx->tbflags = (uint32_t)ctx->base.tb->flags;
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ctx->envflags = ctx->base.tb->flags & TB_FLAG_ENVFLAGS_MASK;
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ctx->memidx = (ctx->tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
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/* We don't know if the delayed pc came from a dynamic or static branch,
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so assume it is a dynamic branch. */
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ctx.delayed_pc = -1; /* use delayed pc from env pointer */
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ctx.base.tb = tb;
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ctx.base.singlestep_enabled = cs->singlestep_enabled;
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ctx.features = env->features;
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ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
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ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&
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(ctx.tbflags & (1 << SR_RB))) * 0x10;
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ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0;
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max_insns = tb_cflags(tb) & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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max_insns = MIN(max_insns, TCG_MAX_INSNS);
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ctx->delayed_pc = -1; /* use delayed pc from env pointer */
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ctx->features = env->features;
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ctx->has_movcal = (ctx->tbflags & TB_FLAG_PENDING_MOVCA);
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ctx->gbank = ((ctx->tbflags & (1 << SR_MD)) &&
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(ctx->tbflags & (1 << SR_RB))) * 0x10;
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ctx->fbank = ctx->tbflags & FPSCR_FR ? 0x10 : 0;
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/* Since the ISA is fixed-width, we can bound by the number
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of instructions remaining on the page. */
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num_insns = -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2;
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max_insns = MIN(max_insns, num_insns);
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/* Single stepping means just that. */
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if (ctx.base.singlestep_enabled || singlestep) {
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max_insns = 1;
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}
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gen_tb_start(tb);
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num_insns = 0;
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bound = -(ctx->base.pc_next | TARGET_PAGE_MASK) / 2;
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ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
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}
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static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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{
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#ifdef CONFIG_USER_ONLY
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if (ctx.tbflags & GUSA_MASK) {
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num_insns = decode_gusa(&ctx, env, &max_insns);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUSH4State *env = cs->env_ptr;
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if (ctx->tbflags & GUSA_MASK) {
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ctx->base.num_insns = decode_gusa(ctx, env, &ctx->base.max_insns);
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}
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#endif
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}
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while (ctx.base.is_jmp == DISAS_NEXT
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&& num_insns < max_insns
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&& !tcg_op_buf_full()) {
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tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags);
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num_insns++;
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static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {
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/* We have hit a breakpoint - make sure PC is up-to-date */
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gen_save_cpu_state(&ctx, true);
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gen_helper_debug(cpu_env);
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ctx.base.is_jmp = DISAS_NORETURN;
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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ctx.base.pc_next += 2;
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break;
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}
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tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);
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}
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if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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gen_io_start();
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}
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static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
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const CPUBreakpoint *bp)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
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decode_opc(&ctx);
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ctx.base.pc_next += 2;
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}
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if (tb_cflags(tb) & CF_LAST_IO) {
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gen_io_end();
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}
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/* We have hit a breakpoint - make sure PC is up-to-date */
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gen_save_cpu_state(ctx, true);
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gen_helper_debug(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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ctx->base.pc_next += 2;
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return true;
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}
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if (ctx.tbflags & GUSA_EXCLUSIVE) {
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static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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CPUSH4State *env = cs->env_ptr;
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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decode_opc(ctx);
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ctx->base.pc_next += 2;
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}
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static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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if (ctx->tbflags & GUSA_EXCLUSIVE) {
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/* Ending the region of exclusivity. Clear the bits. */
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ctx.envflags &= ~GUSA_MASK;
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ctx->envflags &= ~GUSA_MASK;
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}
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switch (ctx.base.is_jmp) {
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switch (ctx->base.is_jmp) {
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case DISAS_STOP:
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gen_save_cpu_state(&ctx, true);
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if (ctx.base.singlestep_enabled) {
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gen_save_cpu_state(ctx, true);
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if (ctx->base.singlestep_enabled) {
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gen_helper_debug(cpu_env);
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} else {
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tcg_gen_exit_tb(0);
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}
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break;
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case DISAS_NEXT:
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gen_save_cpu_state(&ctx, false);
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gen_goto_tb(&ctx, 0, ctx.base.pc_next);
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case DISAS_TOO_MANY:
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gen_save_cpu_state(ctx, false);
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gen_goto_tb(ctx, 0, ctx->base.pc_next);
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break;
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case DISAS_NORETURN:
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break;
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default:
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g_assert_not_reached();
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}
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}
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gen_tb_end(tb, num_insns);
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static void sh4_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
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{
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qemu_log("IN:\n"); /* , lookup_symbol(dcbase->pc_first)); */
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log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
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}
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tb->size = ctx.base.pc_next - pc_start;
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tb->icount = num_insns;
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static const TranslatorOps sh4_tr_ops = {
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.init_disas_context = sh4_tr_init_disas_context,
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.tb_start = sh4_tr_tb_start,
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.insn_start = sh4_tr_insn_start,
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.breakpoint_check = sh4_tr_breakpoint_check,
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.translate_insn = sh4_tr_translate_insn,
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.tb_stop = sh4_tr_tb_stop,
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.disas_log = sh4_tr_disas_log,
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};
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(pc_start)) {
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qemu_log_lock();
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qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
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log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start);
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qemu_log("\n");
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qemu_log_unlock();
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}
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#endif
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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{
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DisasContext ctx;
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translator_loop(&sh4_tr_ops, &ctx.base, cs, tb);
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}
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void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
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