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target/ppc: Fix eieio memory ordering semantics 

The generated eieio memory ordering semantics do not match the
instruction definition in the architecture. Add a big comment to
explain this strange instruction and correct the memory ordering
behaviour.

Signed-off: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Nicholas Piggin 2022-05-19 23:59:05 +10:00 committed by Daniel Henrique Barboza
parent 6f52f731a6
commit fcb830af30
1 changed files with 26 additions and 1 deletions
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27
target/ppc/translate.c
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@ -3513,7 +3513,32 @@ static void gen_stswx(DisasContext *ctx)
/* eieio */ /* eieio */
static void gen_eieio(DisasContext *ctx) static void gen_eieio(DisasContext *ctx)
{ {
TCGBar bar = TCG_MO_LD_ST; TCGBar bar = TCG_MO_ALL;
/*
* eieio has complex semanitcs. It provides memory ordering between
* operations in the set:
* - loads from CI memory.
* - stores to CI memory.
* - stores to WT memory.
*
* It separately also orders memory for operations in the set:
* - stores to cacheble memory.
*
* It also serializes instructions:
* - dcbt and dcbst.
*
* It separately serializes:
* - tlbie and tlbsync.
*
* And separately serializes:
* - slbieg, slbiag, and slbsync.
*
* The end result is that CI memory ordering requires TCG_MO_ALL
* and it is not possible to special-case more relaxed ordering for
* cacheable accesses. TCG_BAR_SC is required to provide this
* serialization.
*/
/* /*
* POWER9 has a eieio instruction variant using bit 6 as a hint to * POWER9 has a eieio instruction variant using bit 6 as a hint to