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target/arm: HVC at EL3 should go to EL3, not EL2 

AArch64 permits code at EL3 to use the HVC instruction; however the
exception we take should go to EL3, not down to EL2 (see the pseudocode
AArch64.CallHypervisor()). Fix the target EL.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20231109151917.1925107-1-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-11-09 15:19:17 +00:00
parent 1d675e59ea
commit fc58891d04
1 changed files with 3 additions and 1 deletions
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4
target/arm/tcg/translate-a64.c
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@ -2351,6 +2351,8 @@ static bool trans_SVC(DisasContext *s, arg_i *a)
static bool trans_HVC(DisasContext *s, arg_i *a) static bool trans_HVC(DisasContext *s, arg_i *a)
{ {
int target_el = s->current_el == 3 ? 3 : 2;
if (s->current_el == 0) { if (s->current_el == 0) {
unallocated_encoding(s); unallocated_encoding(s);
return true; return true;
@ -2363,7 +2365,7 @@ static bool trans_HVC(DisasContext *s, arg_i *a)
gen_helper_pre_hvc(tcg_env); gen_helper_pre_hvc(tcg_env);
/* Architecture requires ss advance before we do the actual work */ /* Architecture requires ss advance before we do the actual work */
gen_ss_advance(s); gen_ss_advance(s);
gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), target_el);
return true; return true;
} }