From fbcbafa2c1c33ae6630e7717f7f4141befb5b31a Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Jul 2020 18:48:18 +0800 Subject: [PATCH] target/riscv: fix vill bit index in vtype register vill bit is at vtype[XLEN-1]. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20200710104920.13550-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eef20ca6e5..a804a5d0ba 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1) +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32];