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target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] 

This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the Secure EL1&0 regime.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-07 14:04:23 +00:00 committed by Peter Maydell
parent 2859d7b590
commit fba37aedec
6 changed files with 25 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/arm/cpu.h
View File

@ -2909,8 +2909,8 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A, ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_0 = 4 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_1 = 5 | ARM_MMU_IDX_A,
ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
@ -2935,8 +2935,8 @@ typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_E10_1 = 1 << 1, ARMMMUIdxBit_E10_1 = 1 << 1,
ARMMMUIdxBit_S1E2 = 1 << 2, ARMMMUIdxBit_S1E2 = 1 << 2,
ARMMMUIdxBit_S1E3 = 1 << 3, ARMMMUIdxBit_S1E3 = 1 << 3,
ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_SE10_0 = 1 << 4,
ARMMMUIdxBit_S1SE1 = 1 << 5, ARMMMUIdxBit_SE10_1 = 1 << 5,
ARMMMUIdxBit_Stage2 = 1 << 6, ARMMMUIdxBit_Stage2 = 1 << 6,
ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MUser = 1 << 0,
ARMMMUIdxBit_MPriv = 1 << 1, ARMMMUIdxBit_MPriv = 1 << 1,

26
target/arm/helper.c
View File

@ -3193,7 +3193,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
mmu_idx = ARMMMUIdx_Stage1_E1; mmu_idx = ARMMMUIdx_Stage1_E1;
break; break;
case 1: case 1:
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -3203,13 +3203,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
/* stage 1 current state PL0: ATS1CUR, ATS1CUW */ /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
switch (el) { switch (el) {
case 3: case 3:
mmu_idx = ARMMMUIdx_S1SE0; mmu_idx = ARMMMUIdx_SE10_0;
break; break;
case 2: case 2:
mmu_idx = ARMMMUIdx_Stage1_E0; mmu_idx = ARMMMUIdx_Stage1_E0;
break; break;
case 1: case 1:
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -3263,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
case 0: case 0:
switch (ri->opc1) { switch (ri->opc1) {
case 0: /* AT S1E1R, AT S1E1W */ case 0: /* AT S1E1R, AT S1E1W */
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
break; break;
case 4: /* AT S1E2R, AT S1E2W */ case 4: /* AT S1E2R, AT S1E2W */
mmu_idx = ARMMMUIdx_S1E2; mmu_idx = ARMMMUIdx_S1E2;
@ -3276,13 +3276,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
} }
break; break;
case 2: /* AT S1E0R, AT S1E0W */ case 2: /* AT S1E0R, AT S1E0W */
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
break; break;
case 4: /* AT S12E1R, AT S12E1W */ case 4: /* AT S12E1R, AT S12E1W */
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
break; break;
case 6: /* AT S12E0R, AT S12E0W */ case 6: /* AT S12E0R, AT S12E0W */
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0; mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -3945,7 +3945,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
static int vae1_tlbmask(CPUARMState *env) static int vae1_tlbmask(CPUARMState *env)
{ {
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
} else { } else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
} }
@ -3981,7 +3981,7 @@ static int alle1_tlbmask(CPUARMState *env)
* stage 1 translations. * stage 1 translations.
*/ */
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) { } else if (arm_feature(env, ARM_FEATURE_EL2)) {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2;
} else { } else {
@ -8715,9 +8715,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
return 2; return 2;
case ARMMMUIdx_S1E3: case ARMMMUIdx_S1E3:
return 3; return 3;
case ARMMMUIdx_S1SE0: case ARMMMUIdx_SE10_0:
return arm_el_is_aa64(env, 3) ? 1 : 3; return arm_el_is_aa64(env, 3) ? 1 : 3;
case ARMMMUIdx_S1SE1: case ARMMMUIdx_SE10_1:
case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MPrivNegPri:
@ -8856,7 +8856,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{ {
switch (mmu_idx) { switch (mmu_idx) {
case ARMMMUIdx_S1SE0: case ARMMMUIdx_SE10_0:
case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser: case ARMMMUIdx_MUser:
case ARMMMUIdx_MSUser: case ARMMMUIdx_MSUser:
@ -11296,7 +11296,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
} }
if (el < 2 && arm_is_secure_below_el3(env)) { if (el < 2 && arm_is_secure_below_el3(env)) {
return ARMMMUIdx_S1SE0 + el; return ARMMMUIdx_SE10_0 + el;
} else { } else {
return ARMMMUIdx_E10_0 + el; return ARMMMUIdx_E10_0 + el;
} }

4
target/arm/internals.h
View File

@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_MUser: case ARMMMUIdx_MUser:
return false; return false;
case ARMMMUIdx_S1E3: case ARMMMUIdx_S1E3:
case ARMMMUIdx_S1SE0: case ARMMMUIdx_SE10_0:
case ARMMMUIdx_S1SE1: case ARMMMUIdx_SE10_1:
case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSPrivNegPri:
case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSUserNegPri:
case ARMMMUIdx_MSPriv: case ARMMMUIdx_MSPriv:

4
target/arm/translate-a64.c
View File

@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *s)
case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1:
useridx = ARMMMUIdx_E10_0; useridx = ARMMMUIdx_E10_0;
break; break;
case ARMMMUIdx_S1SE1: case ARMMMUIdx_SE10_1:
useridx = ARMMMUIdx_S1SE0; useridx = ARMMMUIdx_SE10_0;
break; break;
case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2:
g_assert_not_reached(); g_assert_not_reached();

6
target/arm/translate.c
View File

@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *s)
case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
case ARMMMUIdx_S1E3: case ARMMMUIdx_S1E3:
case ARMMMUIdx_S1SE0: case ARMMMUIdx_SE10_0:
case ARMMMUIdx_S1SE1: case ARMMMUIdx_SE10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
case ARMMMUIdx_MUser: case ARMMMUIdx_MUser:
case ARMMMUIdx_MPriv: case ARMMMUIdx_MPriv:
return arm_to_core_mmu_idx(ARMMMUIdx_MUser); return arm_to_core_mmu_idx(ARMMMUIdx_MUser);

2
target/arm/translate.h
View File

@ -126,7 +126,7 @@ static inline int default_exception_el(DisasContext *s)
* exceptions can only be routed to ELs above 1, so we target the higher of * exceptions can only be routed to ELs above 1, so we target the higher of
* 1 or the current EL. * 1 or the current EL.
*/ */
return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
? 3 : MAX(1, s->current_el); ? 3 : MAX(1, s->current_el);
} }