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target/ppc: Split out ppc_env_mmu_index 

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-29 10:18:33 +10:00
parent db8b41941a
commit fb00f730c5
4 changed files with 14 additions and 9 deletions
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7
target/ppc/cpu.h
View File

@ -1624,7 +1624,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
/* MMU modes definitions */ /* MMU modes definitions */
#define MMU_USER_IDX 0 #define MMU_USER_IDX 0
static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
{ {
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
return MMU_USER_IDX; return MMU_USER_IDX;
@ -1633,6 +1633,11 @@ static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
#endif #endif
} }
static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
{
return ppc_env_mmu_index(env, ifetch);
}
/* Compatibility modes */ /* Compatibility modes */
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,

2
target/ppc/cpu_init.c
View File

@ -7457,7 +7457,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
"%08x iidx %d didx %d\n", "%08x iidx %d didx %d\n",
env->msr, env->spr[SPR_HID0], env->hflags, env->msr, env->spr[SPR_HID0], env->hflags,
cpu_mmu_index(env, true), cpu_mmu_index(env, false)); ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false));
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
if (env->tb_env) { if (env->tb_env) {
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64

10
target/ppc/mem_helper.c
View File

@ -83,7 +83,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb,
void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
{ {
uintptr_t raddr = GETPC(); uintptr_t raddr = GETPC();
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = ppc_env_mmu_index(env, false);
void *host = probe_contiguous(env, addr, (32 - reg) * 4, void *host = probe_contiguous(env, addr, (32 - reg) * 4,
MMU_DATA_LOAD, mmu_idx, raddr); MMU_DATA_LOAD, mmu_idx, raddr);
@ -105,7 +105,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
{ {
uintptr_t raddr = GETPC(); uintptr_t raddr = GETPC();
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = ppc_env_mmu_index(env, false);
void *host = probe_contiguous(env, addr, (32 - reg) * 4, void *host = probe_contiguous(env, addr, (32 - reg) * 4,
MMU_DATA_STORE, mmu_idx, raddr); MMU_DATA_STORE, mmu_idx, raddr);
@ -135,7 +135,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
return; return;
} }
mmu_idx = cpu_mmu_index(env, false); mmu_idx = ppc_env_mmu_index(env, false);
host = probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr); host = probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr);
if (likely(host)) { if (likely(host)) {
@ -224,7 +224,7 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
return; return;
} }
mmu_idx = cpu_mmu_index(env, false); mmu_idx = ppc_env_mmu_index(env, false);
host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr); host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr);
if (likely(host)) { if (likely(host)) {
@ -276,7 +276,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr,
target_ulong mask, dcbz_size = env->dcache_line_size; target_ulong mask, dcbz_size = env->dcache_line_size;
uint32_t i; uint32_t i;
void *haddr; void *haddr;
int mmu_idx = epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); int mmu_idx = epid ? PPC_TLB_EPID_STORE : ppc_env_mmu_index(env, false);
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
/* Check for dcbz vs dcbzl on 970 */ /* Check for dcbz vs dcbzl on 970 */

4
target/ppc/mmu_common.c
View File

@ -1561,9 +1561,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
* mapped by code TLBs, so we also try a MMU_INST_FETCH. * mapped by code TLBs, so we also try a MMU_INST_FETCH.
*/ */
if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p,
cpu_mmu_index(&cpu->env, false), false) || ppc_env_mmu_index(&cpu->env, false), false) ||
ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p,
cpu_mmu_index(&cpu->env, true), false)) { ppc_env_mmu_index(&cpu->env, true), false)) {
return raddr & TARGET_PAGE_MASK; return raddr & TARGET_PAGE_MASK;
} }
return -1; return -1;