mirror of https://github.com/xemu-project/xemu.git
hw/arm/smmuv3: Implement MMIO write operations
Now we have relevant helpers for queue and irq management, let's implement MMIO write operations. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-8-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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dadd1a0809
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@ -61,6 +61,8 @@ REG32(CR0, 0x20)
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FIELD(CR0, EVENTQEN, 2, 1)
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FIELD(CR0, CMDQEN, 3, 1)
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#define SMMU_CR0_RESERVED 0xFFFFFC20
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REG32(CR0ACK, 0x24)
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REG32(CR1, 0x28)
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REG32(CR2, 0x2c)
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@ -149,10 +151,6 @@ static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
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return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
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}
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/* public until callers get introduced */
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void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
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void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
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/* Queue Handling */
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#define Q_BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK)
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@ -314,6 +312,6 @@ enum { /* Command completion notification */
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addr; \
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})
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int smmuv3_cmdq_consume(SMMUv3State *s);
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#define SMMU_FEATURE_2LVL_STE (1 << 0)
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#endif
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170
hw/arm/smmuv3.c
170
hw/arm/smmuv3.c
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@ -38,7 +38,8 @@
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* @irq: irq type
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* @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
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*/
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void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
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static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq,
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uint32_t gerror_mask)
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{
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bool pulse = false;
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@ -75,7 +76,7 @@ void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
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}
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}
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void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
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static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
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{
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uint32_t pending = s->gerror ^ s->gerrorn;
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uint32_t toggled = s->gerrorn ^ new_gerrorn;
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@ -174,7 +175,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
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s->sid_split = 0;
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}
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int smmuv3_cmdq_consume(SMMUv3State *s)
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static int smmuv3_cmdq_consume(SMMUv3State *s)
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{
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SMMUCmdError cmd_error = SMMU_CERROR_NONE;
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SMMUQueue *q = &s->cmdq;
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@ -270,11 +271,170 @@ int smmuv3_cmdq_consume(SMMUv3State *s)
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return 0;
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}
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static MemTxResult smmu_writell(SMMUv3State *s, hwaddr offset,
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uint64_t data, MemTxAttrs attrs)
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{
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switch (offset) {
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case A_GERROR_IRQ_CFG0:
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s->gerror_irq_cfg0 = data;
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return MEMTX_OK;
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case A_STRTAB_BASE:
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s->strtab_base = data;
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return MEMTX_OK;
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case A_CMDQ_BASE:
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s->cmdq.base = data;
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s->cmdq.log2size = extract64(s->cmdq.base, 0, 5);
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if (s->cmdq.log2size > SMMU_CMDQS) {
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s->cmdq.log2size = SMMU_CMDQS;
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}
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return MEMTX_OK;
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case A_EVENTQ_BASE:
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s->eventq.base = data;
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s->eventq.log2size = extract64(s->eventq.base, 0, 5);
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if (s->eventq.log2size > SMMU_EVENTQS) {
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s->eventq.log2size = SMMU_EVENTQS;
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}
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return MEMTX_OK;
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case A_EVENTQ_IRQ_CFG0:
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s->eventq_irq_cfg0 = data;
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return MEMTX_OK;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 64-bit access to 0x%"PRIx64" (WI)\n",
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__func__, offset);
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return MEMTX_OK;
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}
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}
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static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
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uint64_t data, MemTxAttrs attrs)
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{
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switch (offset) {
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case A_CR0:
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s->cr[0] = data;
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s->cr0ack = data & ~SMMU_CR0_RESERVED;
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/* in case the command queue has been enabled */
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smmuv3_cmdq_consume(s);
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return MEMTX_OK;
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case A_CR1:
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s->cr[1] = data;
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return MEMTX_OK;
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case A_CR2:
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s->cr[2] = data;
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return MEMTX_OK;
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case A_IRQ_CTRL:
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s->irq_ctrl = data;
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return MEMTX_OK;
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case A_GERRORN:
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smmuv3_write_gerrorn(s, data);
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/*
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* By acknowledging the CMDQ_ERR, SW may notify cmds can
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* be processed again
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*/
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smmuv3_cmdq_consume(s);
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG0: /* 64b */
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s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 0, 32, data);
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG0 + 4:
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s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 32, 32, data);
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG1:
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s->gerror_irq_cfg1 = data;
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG2:
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s->gerror_irq_cfg2 = data;
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return MEMTX_OK;
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case A_STRTAB_BASE: /* 64b */
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s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
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return MEMTX_OK;
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case A_STRTAB_BASE + 4:
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s->strtab_base = deposit64(s->strtab_base, 32, 32, data);
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return MEMTX_OK;
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case A_STRTAB_BASE_CFG:
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s->strtab_base_cfg = data;
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if (FIELD_EX32(data, STRTAB_BASE_CFG, FMT) == 1) {
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s->sid_split = FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT);
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s->features |= SMMU_FEATURE_2LVL_STE;
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}
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return MEMTX_OK;
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case A_CMDQ_BASE: /* 64b */
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s->cmdq.base = deposit64(s->cmdq.base, 0, 32, data);
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s->cmdq.log2size = extract64(s->cmdq.base, 0, 5);
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if (s->cmdq.log2size > SMMU_CMDQS) {
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s->cmdq.log2size = SMMU_CMDQS;
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}
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return MEMTX_OK;
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case A_CMDQ_BASE + 4: /* 64b */
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s->cmdq.base = deposit64(s->cmdq.base, 32, 32, data);
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return MEMTX_OK;
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case A_CMDQ_PROD:
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s->cmdq.prod = data;
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smmuv3_cmdq_consume(s);
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return MEMTX_OK;
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case A_CMDQ_CONS:
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s->cmdq.cons = data;
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return MEMTX_OK;
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case A_EVENTQ_BASE: /* 64b */
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s->eventq.base = deposit64(s->eventq.base, 0, 32, data);
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s->eventq.log2size = extract64(s->eventq.base, 0, 5);
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if (s->eventq.log2size > SMMU_EVENTQS) {
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s->eventq.log2size = SMMU_EVENTQS;
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}
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return MEMTX_OK;
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case A_EVENTQ_BASE + 4:
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s->eventq.base = deposit64(s->eventq.base, 32, 32, data);
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return MEMTX_OK;
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case A_EVENTQ_PROD:
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s->eventq.prod = data;
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return MEMTX_OK;
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case A_EVENTQ_CONS:
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s->eventq.cons = data;
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return MEMTX_OK;
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case A_EVENTQ_IRQ_CFG0: /* 64b */
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s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data);
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return MEMTX_OK;
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case A_EVENTQ_IRQ_CFG0 + 4:
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s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data);
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return MEMTX_OK;
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case A_EVENTQ_IRQ_CFG1:
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s->eventq_irq_cfg1 = data;
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return MEMTX_OK;
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case A_EVENTQ_IRQ_CFG2:
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s->eventq_irq_cfg2 = data;
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return MEMTX_OK;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 32-bit access to 0x%"PRIx64" (WI)\n",
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__func__, offset);
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return MEMTX_OK;
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}
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}
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static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t data,
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unsigned size, MemTxAttrs attrs)
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{
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/* not yet implemented */
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return MEMTX_ERROR;
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SMMUState *sys = opaque;
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SMMUv3State *s = ARM_SMMUV3(sys);
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MemTxResult r;
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/* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
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offset &= ~0x10000;
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switch (size) {
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case 8:
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r = smmu_writell(s, offset, data, attrs);
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break;
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case 4:
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r = smmu_writel(s, offset, data, attrs);
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break;
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default:
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r = MEMTX_ERROR;
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break;
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}
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trace_smmuv3_write_mmio(offset, data, size, r);
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return r;
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}
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static MemTxResult smmu_readll(SMMUv3State *s, hwaddr offset,
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@ -23,3 +23,9 @@ smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t con
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smmuv3_cmdq_opcode(const char *opcode) "<--- %s"
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smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d "
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smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error on %s command execution: %d"
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smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d"
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smmuv3_update_check_cmd(int error) "cmdq not enabled or error :0x%x"
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smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
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smmuv3_write_mmio_idr(uint64_t addr, uint64_t val) "write to RO/Unimpl reg 0x%"PRIx64" val64:0x%"PRIx64
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smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
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smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
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