mirror of https://github.com/xemu-project/xemu.git
arm_gic: Rename gic_state to GICState
Rename the gic_state struct to match QEMU's coding style conventions
for structure names, since the impending KVM-for-ARM patches will
create another subclass of it. This patch was created using:
sed -i 's/gic_state/GICState/g' hw/arm_gic.c hw/arm_gic_common.c \
hw/arm_gic_internal.h hw/armv7m_nvic.c
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
fa2ddcb4f5
commit
fae1528675
44
hw/arm_gic.c
44
hw/arm_gic.c
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@ -36,7 +36,7 @@ static const uint8_t gic_id[] = {
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#define NUM_CPU(s) ((s)->num_cpu)
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static inline int gic_get_current_cpu(gic_state *s)
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static inline int gic_get_current_cpu(GICState *s)
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{
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if (s->num_cpu > 1) {
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return cpu_single_env->cpu_index;
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@ -46,7 +46,7 @@ static inline int gic_get_current_cpu(gic_state *s)
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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void gic_update(gic_state *s)
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void gic_update(GICState *s)
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{
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int best_irq;
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int best_prio;
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@ -84,7 +84,7 @@ void gic_update(gic_state *s)
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}
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}
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void gic_set_pending_private(gic_state *s, int cpu, int irq)
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void gic_set_pending_private(GICState *s, int cpu, int irq)
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{
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int cm = 1 << cpu;
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@ -105,7 +105,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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*/
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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int cm, target;
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if (irq < (s->num_irq - GIC_INTERNAL)) {
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/* The first external input line is internal interrupt 32. */
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@ -137,7 +137,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
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gic_update(s);
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}
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static void gic_set_running_irq(gic_state *s, int cpu, int irq)
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static void gic_set_running_irq(GICState *s, int cpu, int irq)
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{
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s->running_irq[cpu] = irq;
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if (irq == 1023) {
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@ -148,7 +148,7 @@ static void gic_set_running_irq(gic_state *s, int cpu, int irq)
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gic_update(s);
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}
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uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
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uint32_t gic_acknowledge_irq(GICState *s, int cpu)
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{
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int new_irq;
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int cm = 1 << cpu;
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@ -167,7 +167,7 @@ uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
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return new_irq;
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}
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void gic_complete_irq(gic_state *s, int cpu, int irq)
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void gic_complete_irq(GICState *s, int cpu, int irq)
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{
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int update = 0;
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int cm = 1 << cpu;
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@ -214,7 +214,7 @@ void gic_complete_irq(gic_state *s, int cpu, int irq)
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static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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{
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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uint32_t res;
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int irq;
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int i;
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@ -347,7 +347,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
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static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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int irq;
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int i;
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int cpu;
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@ -500,7 +500,7 @@ static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
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static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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if (offset == 0xf00) {
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int cpu;
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int irq;
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@ -539,7 +539,7 @@ static const MemoryRegionOps gic_dist_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
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static uint32_t gic_cpu_read(GICState *s, int cpu, int offset)
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{
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switch (offset) {
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case 0x00: /* Control */
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@ -561,7 +561,7 @@ static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
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}
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}
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static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
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static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
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{
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switch (offset) {
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case 0x00: /* Control */
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@ -587,25 +587,25 @@ static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
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static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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return gic_cpu_read(s, gic_get_current_cpu(s), addr);
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}
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static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
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}
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/* Wrappers to read/write the GIC CPU interface for a specific CPU.
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* These just decode the opaque pointer into gic_state* + cpu id.
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* These just decode the opaque pointer into GICState* + cpu id.
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*/
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static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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gic_state **backref = (gic_state **)opaque;
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gic_state *s = *backref;
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GICState **backref = (GICState **)opaque;
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GICState *s = *backref;
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int id = (backref - s->backref);
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return gic_cpu_read(s, id, addr);
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}
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@ -613,8 +613,8 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
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static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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gic_state **backref = (gic_state **)opaque;
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gic_state *s = *backref;
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GICState **backref = (GICState **)opaque;
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GICState *s = *backref;
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int id = (backref - s->backref);
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gic_cpu_write(s, id, addr, value);
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}
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@ -631,7 +631,7 @@ static const MemoryRegionOps gic_cpu_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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void gic_init_irqs_and_distributor(gic_state *s, int num_irq)
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void gic_init_irqs_and_distributor(GICState *s, int num_irq)
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{
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int i;
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@ -657,7 +657,7 @@ static int arm_gic_init(SysBusDevice *dev)
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{
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/* Device instance init function for the GIC sysbus device */
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int i;
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gic_state *s = FROM_SYSBUS(gic_state, dev);
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GICState *s = FROM_SYSBUS(GICState, dev);
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ARMGICClass *agc = ARM_GIC_GET_CLASS(s);
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agc->parent_init(dev);
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@ -701,7 +701,7 @@ static void arm_gic_class_init(ObjectClass *klass, void *data)
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static TypeInfo arm_gic_info = {
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.name = TYPE_ARM_GIC,
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.parent = TYPE_ARM_GIC_COMMON,
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.instance_size = sizeof(gic_state),
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.instance_size = sizeof(GICState),
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.class_init = arm_gic_class_init,
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.class_size = sizeof(ARMGICClass),
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};
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@ -22,7 +22,7 @@
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static void gic_save(QEMUFile *f, void *opaque)
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{
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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int i;
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int j;
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@ -56,7 +56,7 @@ static void gic_save(QEMUFile *f, void *opaque)
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static int gic_load(QEMUFile *f, void *opaque, int version_id)
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{
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gic_state *s = (gic_state *)opaque;
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GICState *s = (GICState *)opaque;
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int i;
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int j;
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@ -96,7 +96,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
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static int arm_gic_common_init(SysBusDevice *dev)
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{
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gic_state *s = FROM_SYSBUS(gic_state, dev);
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GICState *s = FROM_SYSBUS(GICState, dev);
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int num_irq = s->num_irq;
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if (s->num_cpu > NCPU) {
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@ -123,7 +123,7 @@ static int arm_gic_common_init(SysBusDevice *dev)
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static void arm_gic_common_reset(DeviceState *dev)
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{
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gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev));
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GICState *s = FROM_SYSBUS(GICState, sysbus_from_qdev(dev));
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int i;
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memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < s->num_cpu; i++) {
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@ -147,13 +147,13 @@ static void arm_gic_common_reset(DeviceState *dev)
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}
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static Property arm_gic_common_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
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DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
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/* Revision can be 1 or 2 for GIC architecture specification
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* versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
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* (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
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*/
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DEFINE_PROP_UINT32("revision", gic_state, revision, 1),
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DEFINE_PROP_UINT32("revision", GICState, revision, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -170,7 +170,7 @@ static void arm_gic_common_class_init(ObjectClass *klass, void *data)
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static TypeInfo arm_gic_common_type = {
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.name = TYPE_ARM_GIC_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(gic_state),
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.instance_size = sizeof(GICState),
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.class_size = sizeof(ARMGICCommonClass),
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.class_init = arm_gic_common_class_init,
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.abstract = true,
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@ -69,7 +69,7 @@ typedef struct gic_irq_state {
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unsigned trigger:1; /* nonzero = edge triggered. */
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} gic_irq_state;
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typedef struct gic_state {
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typedef struct GICState {
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SysBusDevice busdev;
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qemu_irq parent_irq[NCPU];
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int enabled;
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@ -92,25 +92,25 @@ typedef struct gic_state {
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/* This is just so we can have an opaque pointer which identifies
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* both this GIC and which CPU interface we should be accessing.
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*/
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struct gic_state *backref[NCPU];
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struct GICState *backref[NCPU];
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MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
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uint32_t num_irq;
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uint32_t revision;
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} gic_state;
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} GICState;
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/* The special cases for the revision property: */
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#define REV_11MPCORE 0
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#define REV_NVIC 0xffffffff
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void gic_set_pending_private(gic_state *s, int cpu, int irq);
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uint32_t gic_acknowledge_irq(gic_state *s, int cpu);
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void gic_complete_irq(gic_state *s, int cpu, int irq);
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void gic_update(gic_state *s);
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void gic_init_irqs_and_distributor(gic_state *s, int num_irq);
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void gic_set_pending_private(GICState *s, int cpu, int irq);
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uint32_t gic_acknowledge_irq(GICState *s, int cpu);
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void gic_complete_irq(GICState *s, int cpu, int irq);
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void gic_update(GICState *s);
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void gic_init_irqs_and_distributor(GICState *s, int num_irq);
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#define TYPE_ARM_GIC_COMMON "arm_gic_common"
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#define ARM_GIC_COMMON(obj) \
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OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC_COMMON)
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OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
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#define ARM_GIC_COMMON_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
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#define ARM_GIC_COMMON_GET_CLASS(obj) \
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@ -122,7 +122,7 @@ typedef struct ARMGICCommonClass {
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#define TYPE_ARM_GIC "arm_gic"
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#define ARM_GIC(obj) \
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OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC)
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OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
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#define ARM_GIC_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC)
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#define ARM_GIC_GET_CLASS(obj) \
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@ -17,7 +17,7 @@
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#include "arm_gic_internal.h"
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typedef struct {
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gic_state gic;
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GICState gic;
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struct {
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uint32_t control;
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uint32_t reload;
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@ -505,9 +505,9 @@ static void armv7m_nvic_instance_init(Object *obj)
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* than our superclass. This function runs after qdev init
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* has set the defaults from the Property array and before
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* any user-specified property setting, so just modify the
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* value in the gic_state struct.
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* value in the GICState struct.
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*/
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gic_state *s = ARM_GIC_COMMON(obj);
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GICState *s = ARM_GIC_COMMON(obj);
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/* The ARM v7m may have anything from 0 to 496 external interrupt
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* IRQ lines. We default to 64. Other boards may differ and should
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* set the num-irq property appropriately.
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