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target-xtensa: fix extui shift amount 

extui opcode only uses lowermost op1 bit for sa4.

Reported-by: malc <av1474@comtv.ru>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: malc <av1474@comtv.ru>
This commit is contained in:
Max Filippov 2012-09-21 02:59:49 +04:00 committed by malc
parent a255066039
commit f9cb5045d1
1 changed files with 21 additions and 3 deletions
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20
target-xtensa/translate.c
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@ -1778,12 +1778,30 @@ static void disas_xtensa_insn(DisasContext *dc)
case 5: case 5:
gen_window_check2(dc, RRR_R, RRR_T); gen_window_check2(dc, RRR_R, RRR_T);
{ {
int shiftimm = RRR_S | (OP1 << 4); int shiftimm = RRR_S | ((OP1 & 1) << 4);
int maskimm = (1 << (OP2 + 1)) - 1; int maskimm = (1 << (OP2 + 1)) - 1;
TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp = tcg_temp_new_i32();
if (shiftimm) {
tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
} else {
tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
}
switch (maskimm) {
case 0xff:
tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
break;
case 0xffff:
tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
break;
default:
tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
break;
}
tcg_temp_free(tmp); tcg_temp_free(tmp);
} }
break; break;