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target/arm: Convert CBZ, CBNZ to decodetree 

Convert the compare-and-branch-immediate insns CBZ and CBNZ
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-15-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-05-12 15:41:00 +01:00
parent 6201b2a4d0
commit f8977d50fc
2 changed files with 11 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
target/arm/tcg/a64.decode
View File

@ -113,3 +113,8 @@ EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
B 0 00101 .......................... @branch B 0 00101 .......................... @branch
BL 1 00101 .......................... @branch BL 1 00101 .......................... @branch
%imm19 5:s19 !function=times_4
&cbz rt imm sf nz
CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19

26
target/arm/tcg/translate-a64.c
View File

@ -1334,33 +1334,22 @@ static bool trans_BL(DisasContext *s, arg_i *a)
return true; return true;
} }
/* Compare and branch (immediate)
* 31 30 25 24 23 5 4 0 static bool trans_CBZ(DisasContext *s, arg_cbz *a)
* +----+-------------+----+---------------------+--------+
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
* +----+-------------+----+---------------------+--------+
*/
static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
{ {
unsigned int sf, op, rt;
int64_t diff;
DisasLabel match; DisasLabel match;
TCGv_i64 tcg_cmp; TCGv_i64 tcg_cmp;
sf = extract32(insn, 31, 1); tcg_cmp = read_cpu_reg(s, a->rt, a->sf);
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
rt = extract32(insn, 0, 5);
diff = sextract32(insn, 5, 19) * 4;
tcg_cmp = read_cpu_reg(s, rt, sf);
reset_btype(s); reset_btype(s);
match = gen_disas_label(s); match = gen_disas_label(s);
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_gen_brcondi_i64(a->nz ? TCG_COND_NE : TCG_COND_EQ,
tcg_cmp, 0, match.label); tcg_cmp, 0, match.label);
gen_goto_tb(s, 0, 4); gen_goto_tb(s, 0, 4);
set_disas_label(s, match); set_disas_label(s, match);
gen_goto_tb(s, 1, diff); gen_goto_tb(s, 1, a->imm);
return true;
} }
/* Test and branch (immediate) /* Test and branch (immediate)
@ -2408,9 +2397,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
static void disas_b_exc_sys(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
{ {
switch (extract32(insn, 25, 7)) { switch (extract32(insn, 25, 7)) {
case 0x1a: case 0x5a: /* Compare & branch (immediate) */
disas_comp_b_imm(s, insn);
break;
case 0x1b: case 0x5b: /* Test & branch (immediate) */ case 0x1b: case 0x5b: /* Test & branch (immediate) */
disas_test_b_imm(s, insn); disas_test_b_imm(s, insn);
break; break;