mirror of https://github.com/xemu-project/xemu.git
hw/block/nvme: add non-mdts command size limit for verify
Verify is not subject to MDTS, so a single Verify command may result in excessive amounts of allocated memory. Impose a limit on the data size by adding support for TP 4040 ("Non-MDTS Command Size Limits"). Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
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3e1da158c4
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@ -23,7 +23,8 @@
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* [pmrdev=<mem_backend_file_id>,] \
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* [pmrdev=<mem_backend_file_id>,] \
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* max_ioqpairs=<N[optional]>, \
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* max_ioqpairs=<N[optional]>, \
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* aerl=<N[optional]>,aer_max_queued=<N[optional]>, \
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* aerl=<N[optional]>,aer_max_queued=<N[optional]>, \
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* mdts=<N[optional]>,zoned.zasl=<N[optional]>, \
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* mdts=<N[optional]>,vsl=<N[optional]>, \
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* zoned.zasl=<N[optional]>, \
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* subsys=<subsys_id>
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* subsys=<subsys_id>
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* -device nvme-ns,drive=<drive_id>,bus=<bus_name>,nsid=<nsid>,\
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* -device nvme-ns,drive=<drive_id>,bus=<bus_name>,nsid=<nsid>,\
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* zoned=<true|false[optional]>, \
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* zoned=<true|false[optional]>, \
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@ -78,12 +79,26 @@
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* as a power of two (2^n) and is in units of the minimum memory page size
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* as a power of two (2^n) and is in units of the minimum memory page size
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* (CAP.MPSMIN). The default value is 7 (i.e. 512 KiB).
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* (CAP.MPSMIN). The default value is 7 (i.e. 512 KiB).
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*
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*
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* - `vsl`
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* Indicates the maximum data size limit for the Verify command. Like `mdts`,
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* this value is specified as a power of two (2^n) and is in units of the
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* minimum memory page size (CAP.MPSMIN). The default value is 7 (i.e. 512
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* KiB).
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*
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* - `zoned.zasl`
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* - `zoned.zasl`
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* Indicates the maximum data transfer size for the Zone Append command. Like
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* Indicates the maximum data transfer size for the Zone Append command. Like
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* `mdts`, the value is specified as a power of two (2^n) and is in units of
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* `mdts`, the value is specified as a power of two (2^n) and is in units of
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* the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.e.
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* the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.e.
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* defaulting to the value of `mdts`).
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* defaulting to the value of `mdts`).
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*
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*
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* - `zoned.append_size_limit`
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* The maximum I/O size in bytes that is allowed in Zone Append command.
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* The default is 128KiB. Since internally this this value is maintained as
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* ZASL = log2(<maximum append size> / <page size>), some values assigned
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* to this property may be rounded down and result in a lower maximum ZA
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* data size being in effect. By setting this property to 0, users can make
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* ZASL to be equal to MDTS. This property only affects zoned namespaces.
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*
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* nvme namespace device parameters
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* nvme namespace device parameters
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* - `subsys`
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* - `subsys`
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@ -2544,6 +2559,10 @@ static uint16_t nvme_verify(NvmeCtrl *n, NvmeRequest *req)
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}
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}
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}
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}
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if (len > n->page_size << n->params.vsl) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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status = nvme_check_bounds(ns, slba, nlb);
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status = nvme_check_bounds(ns, slba, nlb);
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if (status) {
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if (status) {
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trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
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trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
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@ -4109,12 +4128,14 @@ static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n, NvmeRequest *req)
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{
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{
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NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
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NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
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uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {};
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uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {};
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NvmeIdCtrlNvm *id_nvm = (NvmeIdCtrlNvm *)&id;
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trace_pci_nvme_identify_ctrl_csi(c->csi);
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trace_pci_nvme_identify_ctrl_csi(c->csi);
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switch (c->csi) {
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switch (c->csi) {
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case NVME_CSI_NVM:
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case NVME_CSI_NVM:
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((NvmeIdCtrlNvm *)&id)->dmrsl = cpu_to_le32(n->dmrsl);
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id_nvm->vsl = n->params.vsl;
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id_nvm->dmrsl = cpu_to_le32(n->dmrsl);
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break;
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break;
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case NVME_CSI_ZONED:
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case NVME_CSI_ZONED:
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@ -5657,6 +5678,11 @@ static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
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"than or equal to mdts (Maximum Data Transfer Size)");
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"than or equal to mdts (Maximum Data Transfer Size)");
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return;
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return;
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}
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}
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if (!n->params.vsl) {
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error_setg(errp, "vsl must be non-zero");
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return;
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}
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}
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}
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static void nvme_init_state(NvmeCtrl *n)
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static void nvme_init_state(NvmeCtrl *n)
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@ -5914,8 +5940,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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id->nn = cpu_to_le32(n->num_namespaces);
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id->nn = cpu_to_le32(n->num_namespaces);
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id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
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id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
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NVME_ONCS_FEATURES | NVME_ONCS_DSM |
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NVME_ONCS_FEATURES | NVME_ONCS_DSM |
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NVME_ONCS_COMPARE | NVME_ONCS_COPY |
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NVME_ONCS_COMPARE | NVME_ONCS_COPY);
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NVME_ONCS_VERIFY);
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/*
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/*
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* NOTE: If this device ever supports a command set that does NOT use 0x0
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* NOTE: If this device ever supports a command set that does NOT use 0x0
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@ -6058,6 +6083,7 @@ static Property nvme_props[] = {
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DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
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DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
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DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
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DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
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DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
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DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
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DEFINE_PROP_UINT8("vsl", NvmeCtrl, params.vsl, 7),
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DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false),
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DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false),
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DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false),
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DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false),
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DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0),
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DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0),
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@ -26,6 +26,7 @@ typedef struct NvmeParams {
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uint8_t aerl;
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uint8_t aerl;
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uint32_t aer_max_queued;
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uint32_t aer_max_queued;
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uint8_t mdts;
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uint8_t mdts;
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uint8_t vsl;
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bool use_intel_id;
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bool use_intel_id;
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uint8_t zasl;
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uint8_t zasl;
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bool legacy_cmb;
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bool legacy_cmb;
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